Interview: Spansion’s CTO Talks About Embedded Charge Trap NOR Flash Technology

Interview: Spansion’s CTO Talks About Embedded Charge Trap NOR Flash Technology

NOR flash is central to embedded applications. It is fast and allows software to run and modify its contents because of its random access mode compared to the block mode NAND flash.

I talked with Dr. Saied Tehrani, Spansion’s Senior Vice President and CTO, about their latest NOR technology, embedded Charge Trap (eCT).

Wong:What is Spansion’s embedded Charge Trap For NOR flash technology?

Tehrani:Spansion eCT technology is an embedded NOR Flash memory based on MirrorBit Charge Trap technology, but modified and optimized for integration with logic. The technology is designed to provide fast access, low power, and a cost effective solution for System-on-Chip (SoC) products that require monolithically integrated Flash memory and high-performance logic.

Wong: How does embedded Charge Trap for NOR work?

Tehrani:Material and physics we utilize for programming and erasing the eCT cell is fundamentally the same as in our MirrorBit technology. The charge-storage memory stores electric charge in the thin nitride based dielectric (Fig. 1). Our MirrorBit operates at 2 bits per cell to provide very efficient memory for high- density products, while our eCT technology relies on a single bit per cell and its architecture allows advantages in read speed and power consumption. eCT technology offers broad temperature range, fast access time (<10ns), low power, and is optimized for ease of integration with high-performance logic and is highly scalable.

Figure 1. Spansion’s embedded Charge Trap (eCT)NOR technology traps electronics in the insulated layer allowing more compact storage cells. Wong: What are the advantages of eCT over other technologies such as Floating Gate?

Tehrani:Charge Trap Technology uses a non-conductive nitride storage layer to trap electrons in place vs. the traditional methods which stores freely moving electrons in a floating-gate which is prone to electron leakage. The Charge Trap technology is simpler, more planar and thus easier to manufacture and integrate with logic. The increased manufacturability results in a more reliable product that is higher performance.

Wong:How does it compare to embedded Charge Trap for NAND flash?

Tehrani:Spansion has also developed a Charge Trap technology for discreet NAND Flash memory, not embedded NAND Flash for logic. This technology and IP is applicable at the 1x nm process node where today’s floating gate technology is expected to run into scaling issue. NOR Flash technology is optimal for embedding with logic because of its inherit fast initial access times and high level of reliability. NAND Flash technology is an order of magnitude slower in initial access and would not provide the performance needed for logic integration.

Wong: What applications does this new technology target?

Tehrani:The applications of Spansion eCT technology are quite broad and diverse. The technology can be easily ported to different process technologies and used with a wide array microcontrollers or System-on-Chip designs for a host of end products that serve automotive, consumer and industrial applications.

Wong: What are Spansion’s plans for eCT technology in its own product portfolio?

Tehrani:Spansion eCT technology is a key enabler for expanding the roadmap of Spansion’s Programmable System Solutions (PSS), which combine Flash memory with configurable logic to enhance processing performance for applications that are memory, processing and MIPS intensive.

The first product in this new PSS portfolio is the Spansion Acoustic Coprocessor which we announced in June 2012. The Spansion Acoustic Coprocessor comprises custom-designed logic and high-speed memory to accelerate and optimize voice-enabled human machine interfaces, while offloading the acoustic processing workload from a conventional CPU.

Wong: What is driving Spansion’s investment in embedded memory technology? Is it needed in the industry?

Tehrani:Many of today’s MCU’s and SoCs integrate some non-volatile memory, however, suppliers are not able to scale the memory cells and its performance to keep pace with their advancements in logic design. The memory expertise to efficiently scale the embedded memory is simply not a capability of many of many logic-design companies. As a result we are seeing the non-volatile memory become a higher percentage of the overall die which results in a sub-optimal logic process and larger, more costly die sizes. Spansion is leveraging its long history in NVM and 10+ years developing Charge Trap Technology for discrete Flash memory to embedded MCUs and SoCs with its Spansion embedded Charge Trap (eCT) technology to help restore the balance between logic and Flash.

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