Electronic Design
Magnetic Cores To MRAM: Nonvolatile Tipping Point?

Magnetic Cores To MRAM: Nonvolatile Tipping Point?

Magnetic core storage used to be everywhere, from mainframes like the Burroughs B5500 (see the figure) to minicomputers. Back then, micros were just a gleam in someone’s eye. These days, 3- by 3-mm, 8- and 16-bit flash micros are the same size as many of the magnetic cores.

Magnetic core memory gave way to a variety of technologies, leading to the current mixture of ROM, EEPROM and nonvolatile RAM (NVRAM), flash memory, SRAM, and dynamic RAM. Life was much easier when only one type of memory was used.

NAND and NOR flash are the mainstays for large-capacity nonvolatile solid-state storage these days. They are even challenging rotating magnetic media as capacities grow and costs fall. NOR flash still has the edge with a much higher capacity limit, but it is getting to the point where more applications can get by with flash capacities and pricing.

The big challenges for flash are wear leveling and write performance. Wear leveling has spawned a host of software and hardware solutions designed to overcome the deficiencies of flash.

NONVOLATILE MEMORY CHALLENGERS

Nonvolatile memory technologies such as magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM), and phase change memory look to challenge flash’s dominance. They may eventually challenge RAM’s cost, capacity, and speed.

Phase change memory from Numonyx (see “Thanks For The Memory”) and Unity Semiconductor are relatively new, but they look to reduce the limitations of flash memories while providing superior performance. Unity Semiconductor’s CMOx phase change memory eliminates the need for a transistor per storage cell (see“Nonvolatile Storage Doesn’t Require Transistors”).

FRAM appears to be taking on applications that currently use EEPROM that come in smaller capacities. Ramtron microcontrollers blend FRAM with flash and SRAM (see “Microcontrollers Commit To FRAM”).

Everspin is now delivering a family of 16-Mbit MRAM chips. Its earlier serial peripheral interface (SPI) and parallel MRAM chips had lower capacities that were suitable for storing configuration information, though these new parts move MRAM into primary storage.

Many applications such as RAID SAS controllers will utilize these chips for large data caches. However, a single 2-Mbyte chip is also sufficient for handling operating systems like Linux. It is actually large enough to handle code and data for a wide range of real-time operating systems (RTOSs) as well.

THE RTOS CONNECTION

The potential movement from data storage to program and data storage moves magnetic memory back to its roots. It is still a long way from the uniform use of core memory within a system. Yet there are significant advantages to nonvolatile storage that operates as fast as SRAM with no write penalty and an unlimited lifetime.

The challenge is whether applications and OSs will coherently address large blocks of nonvolatile storage like MRAM or one of the other challengers. There is already some support for flash within a hierarchical memory environment, but flash often is viewed as block storage. MRAM and RAM can coexist with the same performance features where the only difference is nonvolatility and a higher resistance to alpha particles.

Instant-on and instant-off operation can benefit from nonvolatile storage, though integration with the OS will be necessary to allow applications to take advantage of this memory. This would allow critical data structures and application code to be retained between power cycles.

Simply having the ability to allocate and deallocate nonvolatile memory is just the first step. Applications would need to be written to account for this ability. Likewise, memory allocators and process initiation will need to be adjusted accordingly. The results could be interesting. 

•  Everspin

•  Numonyx

•  Ramtron

•  Unity Semiconductor

TAGS: Digital ICs
Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish