Competitive pressures are forcing designers of consumer electronics such as digital TVs, high-end printers, PCs, digital still cameras, and set-top boxes to lower system costs without sacrificing performance.
To meet these needs, memory manufacturers shrink die sizes, minimize feature sets, and reduce pin counts by multiplexing address and data pins. However, these approaches have failed to satisfy the increasing demand for lower memory subsystem cost and higher system performance.
First-generation Serial Peripheral Interface (SPI) devices were successful in reducing costs but only offered small densities and low performance. Read performance, for example, declined as much as 80% when compared to parallel NOR.
High-end electronics system designers require more memory and the best performance possible to be competitive and innovative. To address this challenge, manufacturers must look at the entire system and not just the individual components. This creates an opportunity for new interfaces in flash memory.
SPI simplifies designs and lowers costs while achieving adequate performance for low-end applications. SPI devices typically read information serially or one bit at a time.
Single-I/O (SIO) SPI is only the beginning. A new level of performance can be achieved with a multiple-I/O (MIO) SPI. An MIO SPI device can support increased bandwidth from the same, low-pin-count SPI device and package.
With multiple I/Os, devices can transmit and receive data either one, two, or four bits at a time, enabling faster speeds while still requiring only eight total pins or six active pins to retain the original benefits of SIO SPI. The enhanced performance means that MIO SPI devices can be used to support faster execution-in-place (XIP) code execution, potentially reducing the amount of RAM required by the system and enabling faster system boot-up times.
A dual-I/O (two-bit data bus) interface enables transfer rates (Fig. 1) to double compared to the standard serial flash memory devices, while a quad-I/O (four-bit data bus) interface improves throughput four times and opens up a much wider range of applications that require higher performance.
SPI flash memories (Table 1) support increasingly higher performance with clock rates up to 104 MHz in SIO mode. When an MIO SPI device is used in quad-mode operation, 80 MHz equates to running the flash at an effective clock frequency of 320 MHz with up to a 40-Mbyte/s continuous transfer rate.
This is more than six times the transfer rate of standard serial flash memories running at a clock rate of 50 MHz. In addition, random access overhead can be reduced by eliminating 28 clock cycles required for each read instruction.
A quad-I/O SPI can enable faster boot times for devices with larger file systems. A 128-Mbit MIO SPI running in quad-I/O mode, with a serial clock (SCK) of 80 MHz, can boot three times faster than a standard 128-Mbit SIO SPI (SCK of 104 MHz). A 128-Mbyte MIO SPI running in quad-I/O mode, with a SCK of 80 MHz, can boot almost four times faster than a standard parallel NOR with a 90-ns initial access time.
THE RIGHT MEMORY SUBSYSTEM
NOR flash memory has grown to a $5 billion market, according to WebFeet (October 2009), and 90% of NOR flash memory revenue shipments today have a parallel NOR interface. Benefits include fast random access and high reliability. Fast random access is best leveraged with broadside addressing architectures where the host presents the byte or word-level random address, and data is available at the I/O about 100 ns later.
Over the past several decades, host ASICs have invested in memory subsystem architectures with parallel NOR to enable XIP for fast boot and memory controller configuration and, in some cases, shadowing code to DRAM for operating-system code execution.
The parallel NOR interface continues to be popular for several reasons. The strong supplier base for parallel NOR flash and a desire by ASIC designers and software architecture designers to protect their investment mean that parallel NOR flash will be around for many years to come.
However, some applications and markets need a new memory solution. For these applications, multi-IO SPI offers a compelling alternative. There is a tremendous level of industry investment to improve the interface to address higher-performance applications. Host designers are evaluating their memory subsystem needs and finding that SPI offers the right balance between fast initial access and high-performance burst-type reads.
Whereas parallel NOR flash has broadside addressing for fast initial access, SPI has a internal multi-bank architecture (Fig. 2) that’s ideal for seamless, continuous-burst applications where code or data can be rapidly streamed into DRAM for host controller access. System designers now have the choice between parallel and serial interfaces based on their memory subsystem architecture needs.
For applications where SPI is the right solution, the switch from a parallel flash memory to SPI affects more than just the flash memory. There are several system level benefits (Table 2) from SPI. First, simpler ASIC memory controller designs result in lower engineering costs and faster time-to-market.
Additionally, SPI yields lower-cost ASICs due to the elimination of approximately 40 pins, while maintaining scalability to higher densities in the future. And finally, it leads to lower-cost printed-circuit boards (PCBs) due to fewer interconnects and less board area from a small SO8 package footprint. In some cases, system designers reduced the PCB from a six-layer board down to a two-layer board.
In addition to the system benefits, the SPI flash component costs can be reduced. The flash die size can be reduced by eliminating approximately 40 bond pads and using simpler SPI peripheral logic on the die. There also is a package cost reduction by reducing pin count and packaging material by approximately 80%.
Another key benefit of SPI is scalability of density without increasing pin count. Parallel flash requires an additional address pin for each successive density. The multiplexed data and I/O structure of SPI allows system designers to support higher-density devices without dedicating additional ASIC address pins.
For example, migrating SPI designs from 32 Mbits to 64 Mbits or 128 Mbits does not require additional address pins, unlike parallel NOR flash. This enables easy density migration for customer board designs and the ability to add more functionality into application code.
DESIGN CYCLES DRIVE SPI ADOPTION
Building in new features to create differentiation and innovation is also easy with an MIO SPI. By reducing pin count, system designers are finding new ways to take advantage of high-performance SPI devices to innovate and add value to their system applications.
Rapid design cycles and the continuous drive to lower system cost are prevalent in the consumer space. There are strong regional influences on the adoption of innovative memory subsystems. Many consumer systems-on-a-chip (SoCs), such as digital TV ASICs, are designed and then assembled into original equipment and design manufacturer reference designs in greater China for the local and export markets. To meet the demands of the consumer market for high performance at the best price point, these designers have embraced and adopted SPI.
There are many examples of how the adoption of SPI is benefiting applications in the consumer space. Digital TV designers use ASIC pins saved by moving from parallel NOR interface to add additional HDMI ports. Multi-function printers take advantage of the x1 SPI interface on eight-pin small-outline IC (SOIC) packages to reduce the cost of printed circuit boards. STB applications migrate from a NOR execute-in-place memory subsystem to an SPI boot and shadow to DRAM model.
MIO SPI flash can improve performance and reduce costs. Design engineers should look to new interfaces in flash memory and explore other possibilities to improve system performance, lower pin count, and lower the overall system cost.