Electronic Design
Possible Differential Path To 20 Gbit/s Memory

Possible Differential Path To 20 Gbit/s Memory

Rambus' Terabyte Bandwidth Initiative (TBI) is an approach to memory interfacing that can address differential and single-ended signaling using the same package. It may allow designers to utilize a memory DIMM that could be used in a range of applications with different transfer characteristics. The differential mode runs at 20 Gbit/s while the single ended mode runs at 12.8 Gbits/s It is designed to use the TSMC 40G process. The FlexMode interface (Fig. 1) is what combines everything into a single package without adding additional pins.

DDR3 currently delivers a bandwidth of about 30 Gbytes/s while GDDR5 is 200 Gbytes/s. This new technology would deliver from 300 to 500 Gbytes/s using DIMMs with the same number of pins. For these rates the system would employ differential signalling on all lines including control and address. It would also use a 32x transfer rate or 20 Gbits/s with a 625 MHz clock. This system, called XDR 2, is the second generation of the XDR memory used with the IBM Cell processor that is found in the Sony PS3.

The FlexMode system utilizes fewer signals for control and address (C/A) versus DDR3 and GDDR5. It actually sends the same amount of information but it does so by running these signals faster. The C/A lines normally used by the single ended are then available for the differential data signals. It is true that that the C/A lines are also differential pairs so there is even a larger reduction, from 31 to 14.

Of course, differential signalling by itself is useful and future designs may use it with a new form factor. In this case, FlexMode is less of an issue but Rambus' differential technology would be applicable.

At this point Rambus is showing off their TBI Multi-Modal Demonstration Platform (Fig. 2). The technology is ready but the initiative is in its infancy. It will take time to see whether this approach will be the next standard.

TAGS: Digital ICs
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