EE Product News

SRAM Boosts Bandwidth & Performance

No-wait read and write cycles at a continuous once-per-clock-cycle rate are possible with the device architecture of the IS61NW6432, a synchronous 64k x 32 SRAM that uses a static RAM architecture developed specifically to allow 100% bus utilization during read-and-write operations. This can increase system bandwidth by as much as 50%, it's claimed, over conventional synchronous SRAMs in typical read-and-write applications.The high-density device has a clock access time of 5 ns, which allows it to support system buses running up to 100 MHz, while its wide 32-bit organization makes it suitable for high-speed networking applications such as switches and routers. Samples are available.

TAGS: Digital ICs
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