Electronic Design

Tool Automates Power Optimization Of Embedded SoC Memories

System-on-a-chip (SoC) design teams have long labored to optimize their creations for power, but doing so in the memory portions of the devices has lagged behind. Today’s memory-IP (intellectual property) providers build complex power-management schemes into their products, yet the design of the control logic to take maximum advantage of these schemes is daunting.

Attempts to get a handle on dynamic power consumption using sleep modes are frequently overlooked due to timeto- market constraints. As a result, embedded SoC memory often can end up consuming up to 70% of the total power budget.

Seeing an opportunity to address this issue, Calypto Design Systems has brought its sequential analysis technology to bear on memory power optimization in the form of its PowerPro MG (memory gating) tool. PowerPro MG inserts sequential memory-gating logic into the design’s original register transfer level (RTL) that takes full advantage of the memory’s built-in power optimization capabilities. This translates into significant reductions in both static and dynamic memory power consumption.

In developing PowerPro MG, Calypto worked closely with Virage Logic to ensure that the tool would support Virage’s 40-nm SiWare memory compilers. The SiWare memories are highly configurable with options to control area, speed, power, and yield. From a power perspective, the memories offer multiple modes: a run mode, a standby mode (light sleep), a shutdown mode, and a dormant mode (deep sleep). “All of these modes are controlled digitally with pins and work nicely with ARM’s Processor Intelligent Power Management,” says Lisa Minwell, Virage Logic’s director of technical marketing.

Driven primarily by array biasing, the memories’ light-sleep mode saves about 50% of static power. The shutdown and deep-sleep modes rely on integrated power switching. The deep-sleep mode comprises turning off power to the memories’ periphery only, which saves some 70% of static power. Shutdown mode kills power to both the periphery and memory array itself, saving 90% of static power.

Where PowerPro MG makes its presence felt, though, is in reduction of dynamic power consumption. As shown by an example of a 1k x 32 Virage Logic 40-nm SiWare memory, the insertion of memory gating extends the amount of time during which the memory is inactive (Fig. 1). In a situation where the Memory Enable pin (ME) is low, or the memory is shut down, for 10% of the time, the bar chart shows total power consumption of about 7200 µW, of which about half is associated with dynamic power.

If PowerPro MG is used to insert memory gating, this ME-low time can be extended from 10% to 50% with a corresponding savings in dynamic power of about 43%. Adding more terms to the memory-gating functionality and extending ME-low time to 80% delivers dynamic power savings of 76%. “We sequentially analyze the design, go back and forth across registers, and find situations in which the memory reads are redundant,” says Tom Sandoval, CEO of Calypto.

During Memory Enable analysis of the design, PowerPro MG can find situations where the ME pin can be shut down more frequently and for longer periods of time. That data is used for implementation of the light-sleep mode. Taking a closer look at light-sleep mode shows that it can be used to reduce leakage power (Fig. 2). “The way people tend to use sleep modes in memories today is to consider the ME pin as corresponding to an idle pin for a functional block,” says Sandoval. “They simply use the pin to shut down memories.”

PowerPro MG adds memory gating to the ME pin so it determines, for individual memories, situations outside of this generic “idle” mode in which there may be opportunities to shut down memories. In this way, the light-sleep modes for each individual memory become more frequent and longer in duration. “This amounts to much finergrained control of memory shutdown,” says Sandoval.

Use of the light-sleep mode for Virage Logic’s memories is not without challenges. Coming out of the lightsleep mode does impose a dynamic power penalty, although PowerPro MG’s sequential analysis and built-in prototyping engine enable the tool to address that issue. A slightly more vexing issue is timing specifications, which must be considered in connection with light-sleep entry and exit. The ME function must be predicted to exit light-sleep mode in time to meet timing requirements.

Also, functional correctness has to be accounted for in applying light-sleep mode. PowerPro MG’s sequential analysis capability again comes into play here, ensuring that memory functionality is not impacted by use of light-sleep mode.

PowerPro MG fits into existing implementation flows. It’s compatible with Linux. A one-year time-based license costs $295,000.

DAVID MALINIAK

CALYPTO DESIGN SYSTEMS
www.calypto.com

VIRAGE LOGIC CORP.
www.viragelogic.com

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