The TMP86CM41F microcontroller with 32 KB of mask ROM and 2 KB of RAM and the TMP86FS41F microcontroller with 60 KB of flash and 2 KB of RAM are designed around firm’s TLCS-870/C core, a modification of the TLCS-870/X core that enables development of lower cost devices and improved C-compiler efficiency. The µCs also offer four channels of 8-bit and two channels of 16-bit timer/counters, a 16-channel, 10-bit ADC, 55 I/O ports, a watchdog timer, PWM output, and a one-channel serial interface (UART). These low power consumers use a design methodology that optimizes clock buffer sizes and clock line lengths while gating the clock to only required circuits. This results in current consumption of 12 mA at 5V and 16 MHz, which is a 40% power savings compared to firm’s TLCS-870/X µCs. In slow mode, current consumption is 30 µA at 5V and 32 kHz. Minimum execution time is 0.25 µs at 5V and 16 MHz or 0.95 µs at 1.8V and 4.2 MHz, allowing high-speed operation with low voltage. The instruction set is optimized for maximum C-compiler efficiency to reduce the object code size produced by the C-compiler by 25% compared to the present TLCS-870, as measured by the firm’s benchmark.
Company: TOSHIBA AMERICA ELECTRONIC COMPONENTS INC. (TAEC)
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