Representing the firm's first foray into the 8051 microcontroller mart, the FlashFlex51 family of MCUs employs an embedded flash memory array mapped into primary and secondary banks and uses a small size sector for both code and data storage. The dual memory bank architecture results in an In-Application Programming (IAP) mode that allows the CPU to run user programs from one bank while concurrently servicing a flash programming operation in the background on the other bank. SST89C54, SST89C58 and SST89C59, the first three members of the FlashFlex51 family, embed 20, 36 and 68 Kbytes of NOR-type SuperFlash EEPROM, respectively. The MCUs' primary memory bank of 16, 32 and 64 Kbytes, with a 128-byte sector size, occupies the internal ROM space for an 8051-compatible µC. The secondary, 4-Kbyte bank with a 64-byte sector size can be used for either electronically erasable data storage or code storage. Other features of the new MCUs include 256 bytes register/data RAM, three 16-bit timer/counters, programmable UART, configurable watch-dog timer, and more. 'C54, 'C58 and 'C59 MCUs are available in 40-pin PDIPs and 44-pin PLCCs and TQFPs.
Company: SILICON STORAGE TECHNOLOGY INC.
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