Wearable technology presents packaging challenges (see “Wearable Technologies Present Packaging Challenges”) but the use of custom ASICs can often reduce the effort needed to create new products. ARM and Imagination MIPS cores are just one way to go. Cortus is another.
Cortus APS23 and APS25 (Fig. 1) 32-bit cores are now available to ASIC designers. These are small cores with a RISC instruction set that includes 16-, 24- and 32-bit instructions. This provides a 16% improvement in code size over their prior cores. The older cores are assembler and C/C++ compatible although the new cores do work with existing Cortus peripheral IP. The new cores also the AXI4 Lite/AXI4 interface. The APS25 supports multicore designs.
The cores are designed to provide security in a connected environment. They support secure execution by keeping secure code in a separate area. Cortus also supports redundancy using lockstep, dual core solutions.
The APS23 is the smaller of the litter with a 3-stage pipeline. It is on part with Cortex-M0/M3 cores. Like the APS25, it supports execution from RAM that is normally faster than flash.
The APS25 has a 5-stage pipeline and address code and data caches. It also runs at 2.5 times the clock speed of the APS23. The APS25 is on par with ARM Cortex-M3/R cores. This core also supports a 16-bit DSP coprocessor. This is done via the extensible instruction set support by both cores.
The cores are supported by a GNU-based tool suite. This includes an Eclipse-based IDE. There are the usual set of profiler and debugging tools included. There is third party support including RTOS support such as FreeRTOS.
ARM has dominated the 32-bit standard core space for a while now but ASIC designers often need an edge. Technology like the Cortus APS23 and APS25 may be what they need.