Electronic Design
High-Performance, Low-Power Cortex-M7 Microcontroller Targets Secure IoT Applications

High-Performance, Low-Power Cortex-M7 Microcontroller Targets Secure IoT Applications

Fig. 11. The STM32H7 is partitioned into three sections for optimized communication and power management.

 

ST Microelectronics' new STM32H7 series is built using 40-nm flash technology and runs at 400 MHz (Fcpu) to deliver high performance with low power requirements. It delivers an EEMBC CoreMark score of 2010. The ARMv7E-M microcontroller is partitioned into three sections (Fig. 1). The peripheral sections operate at 200 MHz (Fcpu/2), with some peripherals operating at 100 MHz (Fcpu/4).

The system uses only 280 µA/MHz in run mode and less than 7 µA in standby mode—8 µA when the 4 Kbyte backup RAM is included. The real-time clock (RTC) adds under 1 µA to standby mode. This is half the power used by the previous generation STM32F7. The STM32H7 batch acquisition mode (BAM) uses only 150 µA/MHz and has a wake-up time of only 70 µs. It takes 405 µs to switch from any stand-by mode to run mode. That 4-Kbyte backup RAM is also protected by tamperproof circuitry.

The chip is available with up to 2 Mbytes of flash memory with ECC (Fig. 2) implemented in a dual-bank configuration, allowing programming of one bank while executing code from the other. This is ideal for remote updates. The RAM also has ECC support. This includes 864 Kbytes of regular RAM, 192 Kbytes of tightly coupled memory (TCM), and L1 caches of 16 Kbytes for instruction and data. There is a 4-Kbyte debug RAM that works in conjunction with the embedded trace module (ETM).

Fig. 22. The STM32H7 incorporates a range of memory including ECC supported dual bank flash, RAM and tightly coupled memory (TCM).

 

The system has a boot loader that is locked down; there will be additional service routines available, as well. The boot loader allows operation with a range of storage devices in addition to the on-chip flash memory. The chips have dual QSPI interfaces as well as two SD/SDIO/MMC interfaces. There is also a memory controller for off-chip SDRAM, NOR, and NAND storage. There is on-chip secure memory for system and user use designed for storing protected cryptographic keys. Flash memory sectors can be marked for protected execution that the memory protection unit (MPU) supports.

Connectivity varies depending upon the chip, but most include support for SPI, I2C, and serial ports. Additional options include Ethernet as well as flexible data-rate CAN (FD-CAN) and time-triggered CAN (TT-CAN) support. USB is in the mix, as well.

The chips include a number of hardware accelerators, such as the dual-precision floating point unit (DP FPU). The Chrom-ART accelerator is for improving 2D graphics performance with a TFT-LCD controllers, and there is a JPEG codec additionally included. The chips have a hardware random number generator (RNG) along with a crypto and hashing accelerator.

Analog peripherals include a 14-bit ADC that handles up to 2 Msamples/s. The ADC has differential inputs and supports a sigma-delta modulator. Chips support a mix of operational amplifiers and comparators.

The STM32H7 includes 10-year support, making it ideal for long-term applications. Software support includes ST’s own development platform that includes the STM32CubeMX configuration code generator. The family also has wide third-party support. it will be supported by ST’s Discovery Board series, as well as other development kits and reference designs.

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