The serial peripheral interface (SPI) bus is a synchronous, full-duplex, serial data link commonly used for the short-distance data exchange between a master device, such as a microcontroller unit (MCU), and one or multiple slave devices, such as data converters, digital I/O devices, temperature sensors, and power management controllers.
When used in its standard configuration, high data rates of up to 20 Mbits/s can be accomplished without jeopardizing synchronicity between clock and data. Modern industrial designs, however, often require the galvanic isolation of the controller from the widely varying ground potentials of the data acquisition and sensor circuitry through digital isolators. These isolators introduce propagation delays that, depending on the interface clock rate, can lead to the loss of synchronicity and, thus, increasing bit-error rates.
SPI uses three interface lines. First, the master initiates the serial interface clock (SCK) to start data transfers. Second, a transmit data line for data is sent from the master to the slave with the designators MOSI (master-out slave-in, the pin-designator at the master side) and SIMO (slave-in master-out, the pin-designator at the slave side). Third, a receive data line for data is sent from the slave to the master with the designators MISO (master-in slave-out, the pin-designator at the master side) and SOMI (slave-out master-in, the pin-designator at the slave side).
The fourth wire commonly associated with the interface is the slave-select signal (/SS). This signal is not required for interface flow control. It is, however, useful for addressing slave devices individually when connected to their chip-enable (/CE) or chip-select (/CS) pins.
Common data rates are in the range of 1 to 20 Mbits/s, and byte lengths can range from 8 bits and 12 bits to multiples of these values. Data transfers always consist of a data exchange. While the master is sending data to the slave, the slave sends data to the master. For that reason the internal shift registers of the master and the slave are set up in a ring formation (Fig. 1).
Prior to a data exchange, the master and slave load their internal shift registers with memory data. Upon a clock signal initiated by the master, the master clocks out its shift register most significant bit (MSB) first via the MOSI line. At the same time the slave reads the first bit from the master at SIMO, latches it into its shift register, and clocks out its MSB via SOMI. The master reads the slave’s first bit at MISO and stores it into memory for later processing. The entire procedure continues until all bits are exchanged and the master idles the clock and disables the slave via /SS.
In addition to setting the clock frequency, the master also configures the clock polarity and phase with respect to the data. These two options, known as CPOL and CPHA, allow for a 180o phase shift of the clock signal and a data delay of half a clock cycle (Fig. 2).
For CPOL = 0, the clock idles at logic zero. If CPHA = 0, data are read on the rising edge and change on the falling edge of SCK. If CPHA = 1, data are read on the falling edge and change on the rising edge of SCK.
For CPOL = 1, the clock idles at logic high. If CPHA = 0, data are read on the falling edge and change on the rising edge of SCK. If CPHA = 1, data are read on the rising edge and change on the falling edge of SCK.
Isolated SPI Bus
The propagation delay of standard SPI configurations presents only a fraction of the clock pulse width. Implementing isolation, however, adds a significant amount of prop-delay to the interface timing (Fig. 3). The only way to make this circuit work is through a drastic reduction in clock frequency and, thus, in data throughput.
Let’s assume that at time X the rising clock edge starts the interface timing and both clock and transmit data from the master arrive equally delayed by the isolator prop-delay at the slave at t = x + tP. Then, after the response time, tRSP, the slave sends its data toward the master, where the receive data also experience a delay through the isolator. Thus, the total delay between the initial clock edge and the receive data is approximately twice the isolator propagation delay (Fig. 4):
tD = 2 • tP + tRSP
Therefore, at high clock rates the synchronicity between clock and receive data is lost. While the slave will still be able to sample the transmit data at the correct time, the master is sampling the receive data at the wrong time. Hence, the loss of synchronicity means loss of data and an increase in bit errors.
One way to maintain synchronicity is the drastic reduction in clock rate until the clock pulse width is extended to approximately twice the propagation delay. To give an example: for a 150-Mbits/s high-speed digital isolator such as the ISO7231M operating at 3.3-V supplies, the maximum prop-delay is 34 ns, which demands a minimum clock pulse width of T/2 = 2 x 34 ns = 68 ns.
In the case of a 50% duty cycle, this pulse width translates to a clock period of 136 ns or a 7.35-MHz clock. Unfortunately, this level of transmission speed totally underutilizes the capabilities of a high-speed isolator. Another method to fully utilize the isolator’s maximum speed capability is the clock loopback method.
Isolated SPI Bus With Clock Loopback
To communicate with SPI peripherals at high speed and/or across long distances, it is necessary to compensate for the propagation delay of the data link. The most commonly applied method is to loop back the master clock via a separate data line, which resembles the receive clock to provide synchronicity for the receive data sent by the slave (Fig. 5).
In transmit direction, the data sent by the master stay in synch with the master clock and can be easily read by the slave. In the opposite or receive direction, data sent by the slave traverse synchronously with the looped-back clock as both experience the same prop-delay through the isolator (Fig. 6).
Because both data streams, in transmit and receive, now possess their own clock to which they run synchronously, the data link is independent of propagation delay and clock speed and allows for maximum speed utilization.
A key requirement of this approach is that the master controller must provide two SPI ports, one of which is programmed in master mode, while the other is programmed in slave mode. Most modern microcontrollers satisfy this requirement by providing two, three, and four SPI ports on a single chip with frequencies well above 20 MHz
However, FPGAs allow for significantly higher clock rates, such as 50 MHz to 100 MHz. This type of speed is commonly required in digital I/O modules with high channel counts where multiple SPIs work in a daisy-chain configuration and fast serial speed is imperative.
SPI is a synchronous, full duplex interface. When confronted with high-speed requirements and long propagation delays, caused by digital isolators or long transmission links, apply the clock-loopback method to ensure reliable interface operation.