Electronic Design
Little Core Shares Big Core Architecture

Little Core Shares Big Core Architecture

Arm announced the high end Cortex-A15 last year (see Arm Delivers More Multicore Multimedia).

This year it has announced the Cortex-A7 MPCore (Fig. 1) that unifies its multicore architectures. The Cortex-A7 MPCore shares the Cortex-A15 architecture and targets low cost, low power multicore applications. In particular, the Cortex-A7 is designed to handle low end smartphones. Like the Cortex-A15, the Cortex-A7 can be used in dual and quad core configurations.

Arm has also coined the phrase "Big.LITTLE Processing" when mixing Cortex-A7 and Cortex-A15 cores. In this case, the Cortex-A7 can handle lower performance chores more efficiently powerwise. The cores are functionally identical so applications can run on either or both depending upon application requirements.

The Cortex-A7 (Fig. 2) uses an in-order, non-symmetric dual-issue processor with a pipeline length of between 8-stages and 10-stages. This is more power efficient but provides lower performance than the Cortex-A15 that has an out-of-order, sustained, triple-issue processor with a pipeline length of between 15-stages and 24-stages. The Cortex-A7 core is also smaller because of this.

Like the Cortex-A15, the Cortex-A7 supports the Thumb-2 instruction set. It has a range of coprocessors and accelerators including NEON Advanced SIMD plus DSP and SIMD extensions. It supports Arm's TrustZone security technology and Jazelle RCT for faster Java execution.

The cores have VFPv4 floating point as we as support for Arm's Large Physical Address Extensions (LPAE). It uses the ARMv7 memory management unit. The hardware virtualization support is key to partitioning runtimes on smartphones.

The Cortex-A7 offers designers a choice even for high end smartphones since putting a single Cortex-A7 MPcore into the mix can potentially provide significant power savings.

TAGS: Digital ICs
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