32-bit ARM Core Targets Midrange Mobile Devices

32-bit ARM Core Targets Midrange Mobile Devices

ARM's latest 32-bit Cortex-A17 (Fig. 1) targets the midrange mobile device space and it supports ARM's big.LITTLE combo with the Cortex-A7 (see Little Core Shares Big Core Architecture) as well as ARM's Mali graphics support. This latest platform address the same space as the earlier Cortex-A12 (see ARM Fills In Midrange With Cortex-A12). It delivers an additional 60% performance boost compared to the Cortex-A9. It will be available in 2015.

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Figure 1. ARM's latest Cortex-A17 is available in quad core configurations that can be paired with Cortex-A7 cores in a big.LITTLE configuration.

The Cortex-A17 is built on the ARMv7-A architecture. The 64-bit Cortex-A50 series is based on the ARMv8 architecture (see Delivering 64-Bit Arm Platforms). The 64-bit systems are upward compatible. The ARMv7-A architecture uses an 11+ stage, out-of-order CPU pipeline. It supports ARM's CoreSight trace debugging as well as hypervisor debugging instructions. The Cortex-A17 has VFPv4 floating point support as well as ARM's TrustZone security technology, NEON advanced SIMD support as well as DSP and SIMD enhancements.

The Cortex-A17 is closest to the Cortex-A12 in design and performance. The biggest difference is the Cortex-A17's support for big.LITTLE. Systems with one to four Cortex-A17 cores are possible. The system has a low-latency L2 cache and cores are tied together using a high-bandwidth AMBA 4 ACE Coherent Bus. Initial implementations of 2 GHz Cortex-A17 are expected to using 28-nm technology while moving to 20-nm.

The Cortex-A17 can be paired with third party graphics and GPU support but it can also be integrated with ARM's Mali options including the Mali-T720 GPU, Mali-V5000 and Mali-DP500 Display support. The Mali-T720 GPU supports the Khronos Group's Adaptive Scalable Texture Compress (ASTC) the reduces data size (see Khronos Releases ASTC Next-Generation Texture Compression Specification). The Cortex-A17 is also supported by ARM's Processor Optimization Pack (POP) IP.

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