Intel’s Silvermont Architecture Targets Low-Power Applications

Intel’s Silvermont Architecture Targets Low-Power Applications

The Intel Silvermont architecture will be delivered on the company’s 22-nm Tri-Gate transistor technology (see “Moore’s Law Continues With 22-nm 3D Transistors” at electronicdesign.com). Silvermont increases peak performance by a factor of three over current Atom technology while reducing power requirements by a factor for five when delivering the same performance. The architecture targets applications that Arm has currently dominated. It will also take over in areas where the Atom has been strong, including microservers.

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Intel is also promising to churn out a new version every year, which would beat the current tick-tock cycle. A number of Silvermont system-on-chip solutions should be available before the end of the year. The Avoton series targets microservers. Rangeley is optimized for communication infrastructure applications. The Baytrail version of Silvermont targets larger mobile devices like tablets. And, Merrifield is for smaller devices like smart phones.

The Silvermont is designed to scale to eight cores. One big change is the move to out-of-order execution (see the figure). Intel has plenty of experience here with its higher-end processors. This will improve single-core performance. Out-of-order execution is already used by AMD’s Jaguar core (see “Low-Power, Single-Chip APU Delivers High Performance” at electronicdesign.com) and Arm’s Cortex-A15 (see “Arm Delivers More Multicore Multimedia” at electronicdesign.com).

Figure 1. Intel’s Silvermont core supports out-of-order execution. It can decode two instructions per cycle.

Silvermont will implement more instructions in hardware. It has improved branch prediction support including prediction of indirect branches. Also, its loop stream buffer allows the core to shut down the fetch and decode sections if the loop instructions fit into the buffer, improving performance while reducing power requirements.

Intel is following the pack in moving from symmetric multithreading (SMT), also known as hyperthreading, to a thread per core. This provides a more balanced execution and is better for real-time embedded applications, but it means that a quad-core chip is needed to run four threads. Four cores will be faster than a pair of hyperthreaded cores because a single hyperthreaded core only added a fraction of a core’s performance to the mix.

Intel will pair two cores with a shared L2 cache. Cores also connect to an in-die interconnect (IDI). The IDI is the same that is used on the latest Intel Core processors. It is important in reducing latency with the on-chip memory controller. Older Atoms had a front-side bus (FSB) interface that was slower and did not allow the chips to benefit from the on-chip memory controller. The IDI and processor core clocks are decoupled, allowing more flexibility when the cores are slowed down.

There will be new instructions with the architecture including SSE4.1 and 4.2 extensions and AES-NI encryption. High-end Intel chips will still have an edge on vector calculations with AVX (see “Intel’s AVX Scales To 1024-Bit Vector Math” at electronicdesign.com). AVX tends to be overkill for most embedded applications.

On the other hand, improved virtualization support is part of Silvermont, such as full support for Intel’s VT-x2 suite including extended page table support. This will be handy for microservers and enable better security support using separation hypervisor kernels on smart phones.

Silvermont’s other high-end features include TSC-deadline timer support, which is the third APIC mode that had only been found in newer Intel chips. Real-time instruction tracing is also supported. The facility is very useful in real-time debugging.

The chips will have more power modes. Silvermont will also balance power utilization across the CPU and graphics cores (GFX) in boost mode, which is similar to the Turbo Boost mode on the Core series. The CPUs then will be able to accelerate when the GFX is not running full tilt.

The chips will support the C6 deep sleep mode. In this case, the core is completely shut down. Developers can utilize a range of C6 substates that also control how the L2 cache operates. It can even be shut down.

Silvermont takes direct aim at the 32-bit and future 64-bit Arm-based chips. Intel has the advantage of a tried-and-true 64-bit, virtualized architecture. It can easily run all popular operating systems including Windows, Linux, and variants like Android. Developers will have a more limited selection of chips from Intel compared to the plethora of options and custom chips built around Arm’s architectures.

Silvermont looks to be Intel’s most disruptive technology if it can displace Arm in even a few major accounts. Intel has definitely raised the performance bar while reducing power consumption.

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