PowerShrink has a fivefold reduction in leakage current
Standard SRAM macro performance improved by 300 mV
SuVolta's PowerShrink transistor employs the Deeply Depleted Channel (DDC) structure. It boasts low power and high performance, using an improved planar bulk CMOS transistor that enables it to be built in existing CMOS fabs. It also allows less costly, bulk planar CMOS to take on more expensive and complex technologies like EUV lithography, FD-SOI, and FinFETs.
PowerShrink targets low-power mobile devices, versus Intel's high-performance 3D transistor technology (see "Moore's Law Continues With 22-nm 3D Transistors" at electronicdesign.com). The DDC transistor allows SuVolta to cut power requirements in half while reducing operating voltage (VDD) by up to 30% via dynamic adaptive body biasing, which provides more effective threshold voltage management versus the typical fixed body bias design. The transistor design also allows a 10% increase or more in drive current (IEFF) by increasing channel mobility by 30% or more.
The body biasing takes advantage of the DDC transistor properties. It lets designers correct systematic manufacturing variations, improving overall yield and decreasing VT variation up to 50%. The approach also allows design tradeoffs between sub-1-V threshold voltage and power consumption if performance isn't critical. Alternatively, the designer can select a lower threshold voltage and increased performance if desired. PowerShrink can eliminate the worst-case tail of the transistor VT distribution, which causes most leakage power consumption. It can cut leakage by a factor of five (Fig. 1).
PowerShrink's advantage is better performance with lower voltage and power requirements while making only minor deviations in the production flow. Designers can take existing designs and utilize PowerShrink to gain most of the benefits of the technology. Even more improvements are possible with a few design tweaks for existing products. New designs can easily take advantage of all of PowerShrink's enhancements.
SuVolta's initial demonstration used standard SRAM designs implemented in 65 nm. It delivered the lowest VDD-MIN using standard SRAM macros, 300 mV below the typical SRAM transistor (Fig. 2). SuVolta has already interested the likes of Fujitsu and Broadcom. Fujitsu Semiconductor will be delivering chips based on its 65-nm technology.
If SuVolta continues to deliver on its claims, then PowerShrink could represent a major boost designers looking to follow to Moore's Law. It should scale to 28 nm and below.