The rapid adoption of media-rich applications in portable consumer products is requiring progressively higher memory speeds and capacities, especially for volatile memory that stores data during operation, as in DRAM. The economics of system-on-a-chip (SoC) design and manufacturing are challenging engineers to find new architectural approaches to embedding large blocks of DRAM in a single chip. One attractive path leads off the Moore's Law treadmill to system-in-package (SiP) implementations using stacked die.
With finer process geometries, SoC designs have been expected to embed the memory array on the logic die. Yet each successive generation of media "richness" places more demands on the memory subsystem. Such applications as megapixel image processing require large "chunks" of frame buffer memory.
But these chunks cannot be readily, or economically, embedded. This approach essentially builds a DRAM chip on a logic process. Also, industry estimates show that the cumulative silicon area consumed by memory is over 60% for a typical SoC.
WEIGHING THE FACTORS
Implementing the required memory involves assessment of development risk, production yield, and reliability. At the 90-nm node, the development investment is approximately $25 million per SoC, escalating toward $50 million at 65 nm.
"The costs for ASIC development are growing to over $46 million, with test costs about $2 million of the total," said Nvidia cofounder Chris Malachowsky at the 2006 International Test Conference. This investment has to be rationalized against consumer product cycles and single-digit average selling prices (ASPs). These factors make the economic model of an embedded DRAM approach very challenging.
The SiP approach can dramatically lower the investment and risk profile by separating the logic and memory die, each being manufactured in cost-competitive process technologies. Furthermore, the same SoC can be used with different memory die, so the investment is amortized across many SiP products.
It's commonly asserted that performance and power considerations dictate an embedded memory approach. However, this isn't often the case in the target mobile consumer applications. For example, showing video on a cell-phone screen at 30 fps with VGA resolution requires a memory bandwidth of about 27 Mbytes/s. This is easily achieved with a single-data-rate (SDR) memory, which delivers 400 Mbytes/s at 100 MHz with a 32-bit wide bus.
For power management, the embedded path must address added complications due to leakage, especially when using a leading-edge process technology (e.g., 65 nm). This is mitigated when using a separate memory die, because a mature DRAM process, in which the leakage characteristics are better controlled, can be used.
TACKLING THE CHALLENGES
The major stumbling blocks for using stacked memory have been the cost of delivering fully tested DRAM die (known-good die, or KGD) and the difficulty of ensuring yield and reliability after packaging.
The KGD test costs make up a significant portion of the total cost of ownership of the memory die. This is due to the added complexity of wafer-level testing (burn-in, comprehensive probe testing, etc.). It's also the main reason why a typical KGD costs two or three times more than the corresponding discrete packaged memory.
What's needed is a complete methodology that reduces the cost of producing a high-quality memory die as well as the cost of the SiP as a whole. Such a platform would incorporate a SiP-optimized DRAM design and testing methodology that minimize the cost of producing a reliable KGD. It also would deliver significant cost benefits in wafer-sort without requiring specialized probing hardware while incorporating the ability to do comprehensive memory testing after packaging.
In addition, solutions like this would correlate final test data to the wafer test to reduce memory costs during the product life cycle, without compromising yield and reliability. With a methodology like this, a 16-Mbit DRAM could be integrated into a SiP for only $0.60 today, moving toward $0.50 later in 2007.