Electronic Design

Matsushita Tapes Out 45-nm SoC With Synopsys Platform

Matsushita used Synopsys' IC Compiler for its first 45-nanometer system-on-chip (SoC) design tapeout, which is now entering volume production. The SoC device, which has more than 250 million transistors, integrates three to four times more logic than its predecessor, so Matsushita turned to IC Compiler for its extended physical synthesis (XPS) technology. This technology accelerates timing closure by extending physical synthesis to full place-and-route, according to a Synopsys release. Matsushita also used Synopsys' Design Compiler solution for RTL synthesis, as well as its PrimeTime SI timing analysis solution and its Star-RCXT extraction tool for silicon-accurate sign-off. Matsushita said Synopsys's platforms enabled it to meet its goals for smaller die size and lower power consumption required by its advanced consumer electronics SoC design.

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