Geneva, Switzerland and Oregon, USA: EDA specialists Mentor Graphics and STMicroelectronics have agreed a broad-scoped collaboration to develop design solutions at the 32-nm technology node and down to 20-nm node.
The three-year development project, named DeCADE, seeks to build on advanced design solutions for SoC development for digital and analog design, including system-level approaches, design methodologies, place and route strategies, optical correction for advanced manufacturing, modeling, electrical characterization and parasitic extraction. DeCADE is aimed at providing design solutions for core CMOS technologies as well as for value-added and application-specific derivative technologies that are developed from the core CMOS process.
These projects can make a fundamental difference in chip capability and, performance, as well as in system-solution cost; among the value-added derivative technologies being considered by the DeCADE projects include RF (Radio Frequency) and wireless technologies, as well as 3D Packaging and chip stacking technologies.
"This joint development effort will provide ST with tools to develop state-of-the-art SoCs at 32-nm and below for ST's customers, taking full advantage of the strong Silicon Process, Device Modeling and Design know-how present on the Crolles Site," said Philippe Magarshack, STMicroelectronics General Manager of Central CAD & Design Solutions. "This ST-Mentor Graphics joint effort further reinforces the Crolles cooperative R&D cluster, which already gathers partners that develop and enable low-power SoCs and value-added application-specific technologies and is a great example of a project developed within the framework of the Nano2012 program."
Nano2012 is a strategic R&D program, led by ST, which gathers research institutes and industrial partners and is supported by French national, regional and local authorities. The program aims to create one of the world's most advanced R&D clusters for the development of new generations of semiconductor technology platforms at the nano-electronic level, where the dimensions of the structures used to build the silicon chips are in the order of tens of nanometers.