Düsseldorf, Germany: Toshiba Electronics Europe’s ASIC Foundry Business Unit has announced a new generation of technologies and services for speeding the development and reducing the cost of system-on-a-chip (SoC) RF ICs. The technologies enable ICs with higher reliabilities than traditional system-in-package (SiP) alternatives while a “hybrid” ASIC/COT (customer own tooling) flow model significantly reduces development risk, says Toshiba.
The company’s most recent RF-CMOS technologies and services have been designed to support the integration of RF, analogue, and complex digital baseband and processor functions into a single chip. Consequently, they are suited to fabless chip makers that are striving to deliver solutions for near-field communications (NFC), wide-area networks (WANs), digital broadcast, telemetry, and other wireless communications applications.
Available at the 130-, 90-, 65-, and 40-nm process nodes, Toshiba’s RF technology combines mature baseline CMOS processes with an RF process design kit (PDK). The 130-, 90-, and 65-nm processes are characterized by high ft ratings of 90, 140, and 180 GHz, respectively.
The RF module enables on-chip integration of passive elements such as metal-insulator-metal (MIM) capacitors, junction and MOSFET varactors (deep N-well, single-end and differential), half-turn differential or symmetrical inductors, and mid-range poly resistors with zero temperature coefficients. Junction capacitors and parasitic devices such as NPN transistors are also available.
To speed the development of RF SoCs, customers can choose to use Toshiba’s “hybrid” ASIC/COT model. In this model, the flow is divided into two—one for the digital baseband processor and the other for the analogue and RF elements.