Texas Instruments said it will drive the development and ratification of the IEEE 1149.7 standard, a 2-pin test and debug interface that requires half the number of pins of IEEE 1149.1 boundary-scan technology. In addition to leading the development and adoption of the new standard, TI is working with Freescale Semiconductor, Intel Corp., Lauterbach Datentechnik GmbH, IPExtreme, ASSET InterTech Inc., Corelis, and GlobeTech Solutions to refine and identify implementation challenges, ensuring a streamlined and robust solution is ready for industry wide adoption.
IEEE 1149.7 is a complementary superset of the widely adopted IEEE 1149.1 (JTAG) standard that has been in use for more than two decades. Scheduled for ratification in early 2009, the new standard acts as a port into embedded systems for device manufacturing, testing, and software development during system development.
Since a majority of today’s systems integrate multiple ICs and often have stringent size constraints, reducing the number of pins and traces will help designers meet their smaller form factor goals and allow for additional functional pins and/or lower package cost. Compared to the four pins reserved for IEEE 1149.1, the IEEE 1149.7 standard will use only two pins to handle clocking, control, and data I/O. The lower pin-count configurations will simplify stacked-die configurations and reduce costs.
“Reducing pin count is an important technology to enable advanced mobile devices,” said Rolf Kühnis of Nokia, chairman of the Mobile Industry Processor Interface (MIPI) Test and Debug working group. “IEEE 1149.7 is a standardized, reduced-pin interface that is compatible with existing technologies and addresses multi-chip debug challenges. This is why IEEE 1149.7 is recommended in the MIPI test and debug specifications.”
Texas Instruments
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