One of Taiwan’s major fabs has decided to skip the 22nm process node in favour of going straight to the 20nm node. The Taiwan Semiconductor Manufacturing Company (TSMC) says its move to 20nm will provide customers with a more viable platform for advanced technology designs, better gate density, and chip performance to cost ratios; the company is expected to enter risk production in the second half of 2010.
The technology is based on a planar process with enhanced high-K metal gate, novel strained silicon, and low-resistance copper Ultra-Low-K interconnects.
The technical rationale behind the move is based on the capability of innovative patterning technology and layout design methodologies required at these advanced technology nodes.
“We have reached a point in advanced technology development where we need to be actively concerned about the ROI of advanced technology. We also need to broaden our thinking beyond the process technology barriers that are inherent in every new node,” explained Dr. Shang-yi Chiang, TSMC senior vice president, Research & Development. “Collaborative and co-optimized innovation is required to overcome the technological and economic challenges.”
TSMC is not alone in its adoption of a 20nm approach. Toshiba has worked on a process involving the formation of three layers: epitaxial silicon, carbon-doped silicon, and boron-doped silicon. The top epitaxial layer functions as a low-resistance path for the electrons and the holes; the carbon-doped silicon acts as a defensive layer to prevent impurity diffusion; and the bottom boron-doped layer suppresses any fixed charges.
Toshiba has said that this design provides greater performance compared with conventionally produced channel structures. In addition, it can be deployed with both nMOS and pMOS transistors to configure CMOS devices with a simple process that adds just a few layer-forming steps.
Toshiba's technology, which is applicable to both the nMOS and pMOS transistors of CMOS devices, is seen as one possible way of taking bulk CMOS technology into the 20nm node.
Currently CMOS technology does have physical limits at around the 20nm generation. Degradation in electron mobility in the channel area and variation in threshold voltage occur at that level. The Toshiba approach provides better gate electrode control over the low-resistance area on the surface by obtaining fine switching of the current.