Xilinx, EDA Leaders Team For UHC Design Verification

Xilinx Inc. will collaborate with Cadence, Mentor and Synopsys to address challenges associated with ultra-high capacity FPGA design verification. The companies will design new verification flows in order to maximize ultra high-density designs targeting 65nm FPGAs. The collaboration will focus on expanding coverage, improving simulation runtime, and reducing verification time by building upon existing technologies to develop next-generation verification solutions. The tools and methodologies are expected to be released in the first half of 2008. "With the growing complexity of today's 65nm FPGAs, verification has become a major time-consuming portion of the FPGA design flow," Bruce Talley, vice president of the Design Software Division at Xilinx, said in a statement. "By collaborating with the industry's leading EDA providers, we can develop solutions to address the challenges faced by our customers at 65nm and beyond." According to a company release, Xilinx introduced the industry's first 65nm FPGAs. The Virtex(TM)-5 FPGA platform, which includes devices with up to 330,000 logic cells, 10 Mb on-chip memory, 1,200 I/Os and a host of additional hardened intellectual property (IP) blocks, has been shipping since May 2006.