Accent, ARM, And Cadence Collaborate On Low-Power Design

Accent, ARM, and Cadence Design Systems announced that Accent successfully validated a low-power design flow using the Cadence Encounter digital IC design platform and ARM Artisan physical IP.

The design flow targets low-power IC design and was proven on a design comprising a large portion of a SoC for a wireline application.

Using the ARM Artisan Metro low-power IP with multi-voltage and multi-threshold capabilities, the design was implemented with a multi-supply multi-voltage (MSMV) design flow using three power domains. High-voltage-threshold (low leakage) optimisation was performed on both the MSMV implementation and a baseline implementation with a single-supply voltage to further reduce leakage power.

Compared to the baseline design flow, the low-power design flow reduced dynamic power by 34%. Additionally, the low-voltage section of the design also showed 40% less leakage power than the baseline flow implementation. As a result, Accent was able to perfect a methodology that implements multi-voltage capabilities in new designs as well as compute tradeoffs in power consumption.

"The need to accommodate multiple power domains and multiple voltage levels makes low-power chip design much more complex than normal chip design," explained Claudio Fasce, vice president of Business Area Design and Supply Chain Management Services for Accent. "Using the Cadence Encounter platform and the ARM Metro IP supporting MSMV design, we were able to quickly validate our low-power design flow and significantly improve our overall low-power design methodology. Close collaboration with ARM and Cadence expands our design skills and enables us to deliver better performing devices and greater competitive advantage to our customers."

The Encounter low-power flow provides support for multiple-supply voltage designs. It consists of top-down multi-supply voltage synthesis using Encounter RTL Compiler global synthesis. This is followed by Encounter implementation for low-power and accurate SI- and IR-aware timing sign-off with CeltIC Nanometer Delay Calculator (NDC) and VoltageStorm static and dynamic power analysis.

The ARM Artisan Metro low-power platform provides a solution for dynamic and leakage power reduction, and makes high-density, yield-improved designs possible. The platform includes standard cells, memories, I/Os, and multi-voltage kits. All components take advantage of new process, circuit design, voltage scaling, power-aware EDA tools, and chip-level design techniques so that designers can meet the growing need for power-dissipation control.

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