Wireless Systems Design

Architectures Drive Up Cost And Power Consumption

Current wireless architectures are jeopardizing the future of this industry. Okay, it's true that wireless-transceiver integration has come a long way. For example, it enabled the industry to move away from bulky handsets with large numbers of components and less than impressive performance. Now, we have smaller, faster equipment with more functions and two-thirds the number of components. But these advances have been incremental. They were made by streamlining clever design techniques and advanced semiconductor-manufacturing capabilities.

Today, the situation is at a critical point. The competitive landscape is changing rapidly. The demand for multi-standard handsets is on the rise. Wireless applications are springing up in non-traditional markets. Integration and cost pressures are mounting. Meanwhile, the creation of today's communications devices continues to rely on the same evolutionary techniques and eclectic approaches.

We combine a variety of building materials and mix on-chip and off-chip circuits. And we hang on to challenging packaging methods like LTCC, CSP, and modules. Unfortunately, the current state of wireless-component engineering does not reflect true integration. Rather, it introduces an increasing number of variables. These variables will inevitably lead to higher costs, larger footprints, and more power-hungry solutions. Ultimately, this cobbled-together architecture will fail.

What's the industry to do? The key to delivering a competitive solution hinges on several factors. The industry must deliver quantum-leap technology improvements in size, cost, and power consumption. It also must develop re-usable "building blocks" of intellectual property (IP) that can be quickly tailored for different wireless applications. In addition, the industry must ensure the availability of low-cost, low-risk, silicon-compatible manufacturing technology. This technology will produce the large quantities of wireless units that embed the new technology.

The base technology for this quantum leap already exists. Microelectromechanical systems for wireless applications, or RF MEMS, are recognized as a highly versatile means of miniaturizing and integrating components. But the answer is not the straight replacement of passive components with RF MEMS. To fully leverage RF MEMS, the industry must change circuitry architectures and IP delivery mechanisms. In this way, we can achieve the higher levels of integration needed to significantly slash size and power consumption while enabling cost-effective manufacturing.

These advanced designs must be able to be manufactured at the stringent cost-per-unit levels required by the industry. Engineering teams must therefore look at how they can develop re-usable "RF building blocks." To meet different functionality and performance specifications, such blocks could be tailored for alternate or derivative products. They would be composed of flexible MEMS and IC circuitry elements, which are designed to support multiple wireless standards.

In addition, the blocks would require manufacturing elements that incorporate specific technology-process expertise. For the entrepreneurially minded, such designs could be licensed to multiple systems houses. They would come with design kits and device libraries that target specific foundries. Of course, the IP would be licensed to the RFIC foundries themselves.

The RF and semiconductor industries cannot implement this approach by themselves. The industry will need development teams composed of multidisciplinary groups from the MEMS, RF, and process worlds. Whether they're outsourced or in-house, these groups can help evaluate new architectures. They can examine material properties and compatibilities; the interaction of high-performance device-IC circuitry; and process considerations.

These advances will not arrive all at once. But real products that incorporate the miniaturized technology are quickly making their way to the forefront. For example, one company has developed a MEMS-based microresonator. This microresonator enables the implementation of a unique receiver architecture that shrinks current handset receiver size from 10 cm2 to 1 cm2. At the same time, it cuts power consumption from 50 mW to just 5 mW. What's the anticipated cost difference based on volume production? According to the company, it's $10 for the current-generation receiver versus $1 for the new smaller version.

Does this solution seem far off? The fact is that MEMS process technology, which can take advantage of the existing IC-manufacturing infrastructure, has already been proven over the last 10 years. It offers reliability and high performance to many sectors of the commercial market, including mission-critical and harsh-environment applications. Advanced RFIC manufacturing methods also have demonstrated a strong track record. What's to stop us from meshing the two established technologies for a major architectural benefit? While it won't be a cakewalk, all it takes is the commitment of a market leader.

Didier Lacroix
CEO, Discera, Inc., 755 Phoenix Dr., Ann Arbor, MI 48108; (734) 528-6366, FAX: (734) 528-6367, www.discera.com.

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