Power supplies that use diodes to rectify an ac voltage to obtain a dc voltage must deal with inherent inefficiencies. A standard diode or ultra-fast diode can have a 1-V forward voltage or higher at rated current.
Schottky diodes were an improvement over the standard diode because their forward voltage is lower. But Schottky diodes also start from a fixed forward voltage. Higher efficiencies can be achieved by synchronously switching MOSFET devices to emulate diodes, taking advantage of the FET’s low conduction losses.
Synchronous switching means getting a FET to turn on and off according to the polarity of the ac waveform so it acts as a rectifier. Unlike the situation with the diode, conduction losses depend upon on resistance (RDS(ON)) and current.
Choosing a FET with a low RDS(ON) reduces the forward voltage drop to a fraction of what any diode can achieve. Hence, the synchronous rectifier will have a much lower loss then a diode, helping improve the overall efficiency.
Having to synchronize the FETs complicates the circuit design. This complexity is a better alternative to the added complexity caused by having to remove the heat generated by a diode. With the ever-increasing efficiency requirements, there is no other choice but to use synchronous rectification.
A number of available schemes can drive the FETs. Texas Instruments (TI) has a few reference designs that use this one basic approach. These reference designs also use variations on this basic approach. The drive circuitry presented here is another variation on TI’s basic approach.
The presented circuit was designed for an 18-W power supply. The outputs are ±15 V at 0.6 A with primary, secondary isolation. The input voltage is from 18 to 32 V. The maximum duty cycle, which is 50%, occurs at 15 V. The required turns ratio is 1 to 2, primary to secondary.
This synchronous rectifier circuit uses a single-ended, forward converter topology. It relies on the output voltage of the transformer to drive the FETs. When the primary switch is on, this is not a problem. When the primary switch is off, the transformer must take the entire off time to reset.
To achieve this, an active clamp was used. A TPS2490, with a built-in active clamp function, was used on this design. How an active clamp works can be found in TI’s literature or elsewhere on the Web.
Figure 1 shows a synchronous rectifier circuit in its most basic form. It also shows the intrinsic diodes. When the primary switch is on, Q2 is driven on. When the primary switch is off, the reset voltage of the transformer drives Q1.
If the transformer reset time were shorter than the off time of the primary switch, Q1 would lose drive and the intrinsic diode would have to carry the current. This would defeat the purpose of using a synchronous rectifier, and it’s why the active clamp is used.
For output voltages under 5 V, it may be possible to drive the FETs directly as shown. Above a 5-V output, the peak voltage from the transformer can exceed the maximum gate, source rating of the FETs at maximum input voltage. Therefore, a means of controlling the gate drive voltage is necessary.
The basic concept behind the synchronous rectifier driver is shown in Figure 2. VIN would be the voltage from the transformer’s output. D18 regulates the voltage. Q19 supplies the current boost to the FET’s gate.
DRIVE CIRCUIT TURN-ON
Figure 3 shows the complete circuit for the +15-V output. It doesn’t include added components that aren’t related to the synchronous rectifier, such as snubbers. The components within the dashed lines make up one rectifier. The description will refer only to this rectifier, but the other rectifier operates the same. For simplicity, all losses and forward diode drops will be ignored.
This rectifier is active when the primary switch is on. During this time, NODE_1’s peak voltage range is 36 to 64 V (input voltage times turns ratio). D4 will regulate the voltage to the gate of Q6 minus the base-emitter voltage drop of Q5. Once Q6 is on, only a static voltage must be maintained at Q6 gate to hold Q6 on. Therefore, R2 can be a large value, keeping losses in R2 and D4 to a minimum.
Of course with a large R2, there isn’t enough current to drive Q5 when Q6 is turning on. R1 and C2 provide the added current when the gate of Q6 needs the drive current. To select values for R1 and C2, the amount of gate drive current must be determined. The easiest way to determine drive current is to use Equation 1 where Q is the total gate charge, t is the turn-on time, and I is the necessary drive current.
The specification for Q6 provides a total gate charge of 25 nC. For turn-on time, an assumption of 25 ns was made. This provides a drive current of 1 A. Based on the specification for Q5, a current gain of 50 was used. Therefore, Q5 base requires a drive current of 20 mA.
Using the minimum voltage at NODE_1, R1 = (36 V – 12 V)/20 mA = 1.2k. I chose to use a 1.0k resistor. C2 is chosen to allow a longer time constant then the assumed turn-on time of 25 ns. The time constant of R1 and C2 is 1k × 220 pf = 220 ns.
Based on TI’s reference design, Q5 collector would be tied to NODE_1. (Q4 collector would be tied to NODE_2.) This means Q5 would have to drop the voltage at NODE_1 to 12 V. Q6 requires 6- to 10-V gate voltage to turn fully on. Since the output voltage is 15 V, Q5 collector was connected to the output. Q5 only has to drop the 15 to 12 V versus dropping 32 to 64 V of NODE_1 to 12 V. The power loss in Q5 is significantly lower when Q5 collector is connected to the output.
R5 was added to dampen any resonance that might be present in the Q6 gate circuit, limit the drive current, and reduce dissipation in Q5 by dropping a few extra volts. In theory, with a 12-V drive and only 1 A of drive necessary, a 12-Ω resistor could be used. This assumes the 12-V drive is switched on in zero time. In reality, there is a finite rise time.
So unless R5 is too large, there will never be 12 V across R5. Assuming R5 will only have 6-V peak across it, R5 could be 6 Ω maximum. Also, 2 Ω was chosen because it was low enough to allow enough drive current and some damping. And by allowing more drive current than necessary, it reduces the possibility of problems when powering the prototype for the first time.
DRIVE CIRCUIT TURN-OFF
When the primary switch turns off, the voltage across the transformer collapses and the Q6 gate voltage is discharged through D2, turning Q6 off. Q5 also turns off since its drive network is tied to NODE_1, the same as D2:
VIN × TON = VOFF × TOFF (2)
Equation 2 provides important information needed for the synchronous rectifier circuit during transformer reset. VIN is the voltage across the primary when the primary switch is on. TON is the on time of the switch. VOFF is the reset voltage across the primary of the transformer. And, TOFF is the off time of the primary switch.
When Q6 is off and Q3 is on, the transformer reset voltage must be determined. At low input voltage, the duty cycle is 50%. As a result, the reset voltage, VOFF, is the same as the input voltage, VIN.
At 32 VIN, the duty cycle is 15 VO/64 VPEAK, or about 23%. Plugging values into Equation 2, (32 VIN) × (0.23) = (VOFF) × (1 – 0.23), provides a VOFF voltage of 9.6 V. At 15 VIN, the voltage would be 15 V. Multiplying by the turns ratio, the voltage range at the output of the transformer is –19.2 to –30 V during the primary switch off time.
The reset voltages are half what the forward drive voltages are, but the biasing values were left the same. In choosing values for the forward drive, I chose to use a low current gain value for the transistor. In reality it is much higher for the conditions, so I left the values unchanged.
ISSUES AND CONSIDERATIONS
If the losses were included, the effect would be small. The most noticeable effect would be an increase in the duty cycle to compensate for the voltage drops.
With Q4 and Q5 collector connected to the 15-V output, designers need to be aware of two issues. During startup, until the output voltage is high enough, there is not enough drive to turn on the FETs. During this time, the intrinsic diode will be the rectifier. This is not a problem since startup will only be around 100 ms and there is not much of a load.
The other issue is what happens during a partial overload. This design limits the current through the primary switch. As the load increases, the peak current in the primary switch and the transformer is limited, and the output voltage will start to drop. At some point, the output voltage will be lower than what is necessary to drive the FETs. The intrinsic diodes become the rectifiers, and they will overheat.
This power supply biases the control circuit off the transformer in a manner that allows the bias voltage to track the output voltage. As the output voltage decreases, so does the bias.
When the undervoltage lockout of the control IC is reached, the power supply shuts down, protecting the power supply from this condition. The power supply would try to restart but would shut down due to the overload. In this condition, the off time is much longer than the run time, so the power supply will stay cool.
A SOT32 package was chosen for the npn transistors. SOT32 packages do not dissipate power very well. They happen to work well in this design, but special attention needs to be paid to their dissipation.
With schedule pressures, there is never time to improve a circuit if it performs well during test. This circuit is no exception. As an example, an assumption was made on the switching times, and the values chosen were based on that assumption. Once a prototype is running, based on actual measurements, the chosen values can be tuned to the circuit.
As another example, an assumption was made about how much voltage would be generated by parasitic components. The transistor’s voltage rating was chosen to ensure the parasitic induced voltages would not cause the transistor’s rating to be exceeded. With a working prototype, these voltages could be checked, and lower-voltage transistors could be chosen. This could save on cost and drive requirements.
NEGATIVE VOLTAGE OUTPUT
The positive and negative synchronous rectifier circuit (Fig. 4) is the same except in how the collector of the npn transistors are connected. The peak voltage at NODE_3 will be from –32 to –64 V. To keep the voltage drop across Q9 to a minimum, Q9 collector is connected to the –15-V output.
During transformer reset, NODE_3 will be held at ground when Q7 is on. D6 prevents a reverse voltage from being applied across Q9. For Q8, no other connection could be made to improve its efficiency.