The higher data rates required by new I/Os such as HDMI, SATA, MIPI,and DisplayPort have design engineers considering ways to lower the capacitance of electrostatic-discharge (ESD) protection devices. Manufacturers, however, are keen to provide greater levels of protection due to finer process geometries being more vulnerable to ESD strikes.
With traditional ESD architectures now struggling to offer a suitable degree of protection and support at desired speeds, the design community faces a major dilemma. As a result, engineers are forced to make difficult tradeoffs between system reliability and signal quality, effectively compromising some element of the system’s overall performance. Designing chips that can meet the latest demands for both increased data rates and greater ESD protection has become a difficult task for manufacturers.
Evolving ESD Protection
The ESD protection landscape has undergone a dramatic shift due to the adoption of smaller manufacturing geometries, reduction of on-chip protection, and the changing application environment:
Smaller geometries: As semiconductor process nodes for today’s most advanced application-specific integrated circuits (ASICs) decrease to 90 nm and below, the voltage and current levels at which ESD-related failures can occur also drop. Widespread adoption of high-speed data interfaces adds to the complexity of maintaining signal-integrity levels while ensuring ESD protection. More robust ESD protection typically means higher levels of capacitance, which negatively impacts on the signal-to-noise ratio (SNR), forcing designers to compromise on either one or the other.
Reduction in on-chip protection: Increased susceptibility to ESD damage has been widely publicized. For example, the Industry Council on ESD Target Specifications recently announced a move to reduce the standard level of on-chip ESD protection, making external ESD protection circuits even more critical for adequate system reliability.
Changes to application environment: Notebook PCs, cell phones, MP3 players, digital cameras, and other portable consumer devices all are used in uncontrolled settings (i.e., without employment of wrist-grounding straps or conductive/grounded table surfaces). In these environments, users may touch I/O connector pins while connecting/disconnecting cables. A portable device also can build up a charge during normal usage and then discharge that energy when connected to another device, such as a computer or TV.
Matched impedance along the entire transmission line is a critical factor in high-speed layouts. The characteristic impedance is affected by many variables—these include trace width, board dielectric thickness, board materials, and components on the traces.
The characteristic impedance of a transmission line is the square root of L/C, where L denotes the inductance and C denotes the capacitance. Thus, if capacitance is added at one point, then the impedance will drop at that point. Conversely, if inductance is added, then the impedance will rise. The inclusion of any ESD protection circuit will, due to its own capacitance, affect the impedance of the line. As a result, this must be compensated for through impedance matching.
While the overriding objective of an optimized layout is to match the impedance along the entire line, it’s allowed to be 100 Ω ±15% under the HDMI spec. Any protection device added to the line, whether a diode, varistor, suppressor, or polymer, adds capacitance—not only from the device itself, but also from the pads connecting the device to the printed-circuit board (PCB).
Increased capacitance distorts the signal and can lead to poor video quality and even compliance test failure. For this reason, ESD protection vendors have focused on reducing the capacitance of their devices. However, as already mentioned, this negatively impacts the ESD protection performance. For example, diode capacitance can be reduced by shrinking its size. This can cause the resistance to increase, though, which will result in higher clamping voltages and greater residual current reaching the protected device.
To compensate for the added capacitance of the protection device, system designers will often seek to reduce capacitance elsewhere on the board, or add extra inductance. Typical compensation techniques include:
• Adding a common mode choke or filter: The extra inductance of a choke can offset the ESD device’s capacitance. Unfortunately, adding high-speed common-mode chokes to a design can be quite expensive, and should be avoided if possible.
• Reducing trace widths in area of protection device (increasing inductance of the trace): Often called “trace necking,” this technique can be very effective when only small amounts of compensation are required. However, one limitation arises on thin dielectric boards—if the capacitance of the ESD protection device is too high, it can be difficult to achieve matched impedance.
• Reducing the capacitance under the trace: This can be done by eliminating any ground plane from under the trace and reducing capacitance only in the area of the ESD component.
While each of these techniques has seen success, they are at best sub-optimal due to added design complexity and cost. They require well-controlled design and manufacturing environments, and use of more expensive external components (such as common mode chokes) or more sophisticated PCBs raises the total bill of materials. Another major drawback is that many engineers lack adequate experience in impedance-controlled layout design. This inexperience often results in design errors that snowball development costs and timeframes due to multiple board spins, as well as design and production slips. Finally, many large-scale manufacturers prefer to engage with multiple PCB vendors, making it difficult to guarantee that a single layout will work with all vendors.
A Novel Approach
Given the notable shortcomings of these compensation techniques, semiconductor manufacturers continue to investigate innovative architectures that would assure signal integrity even at the higher data rates now required by the industry. And they’re doing this without the viability of the all-important ESD protection element being brought into question.
One such example is the PicoGuard XS architecture. According to developer ON Semiconductor, it upholds the signal integrity of high-speed data interfaces while enhancing ESD protection. This eliminates trace parasitics by routing up and through the package, rather than under it. It foregoes any form of external compensation by integrating inductors with the ESD diode to match the signal line impedance. The integrated inductors improve ESD performance by lowering the clamping voltage and the residual current seen at the protected ASIC.
The XS package’s structure allows for the ground to be all the way around the underside of the package (Fig. 1). This means that the wire bonding from all of the pads to the die is of the same length, resulting in a matching of the inductance. Thus, the board designer needn’t implement any compensation procedure. Also, in terms of the dynamic resistance (RDYN), products utilizing the PicoGuard XS architecture can outperform other traditional flow-through parts targeted at protecting high-speed differential data lines, says ON Semiconductor.
The architecture eliminates the need for chokes or trace-width modification on the PCB. Furthermore, it doesn’t depend on the board stack-up, allowing system designers to use multiple board vendors without needing to customize impedance matching for each vendor. It’s able to provide matched impedance independent of the number of PCB layers involved, the dielectric thickness, and other layout-specific variables.
Here Comes The Science Bit
Looking at a standard ESD protection device, the inductor element represents the parasitic inductance arising from the bond wire and the PCB trace leading to the protection device (Fig. 2). The inductive element presents high impedance against high-slew-rate ESD strikes, limiting the ability of the protection device to quickly absorb the energy. As a result, more energy reaches the protected ASIC.
In contrast, the inductive elements of the PicoGuard XS architecture are in series with the conduction path leading to the protected ASIC (Fig. 3). The elements actually limit the current and voltage striking the protected device. First, there’s the reactance of inductive element L1 on the connector side that sustains an ESD strike. This acts in the opposite direction of the ESD current, helping limit the peak striking voltage. The reactance of the inductive element L2 on the ASIC side then forces the more limited ESD strike current to be shunted through the ESD protection diodes. At the same time, the voltage drop across both series elements acts to lower the clamping voltage seen at the protected ASIC.
Next-generation electronic devices will have to marry support for high-speed data transmission with strong signal-integrity levels and continued safeguarding from ESD strikes. This calls for a fundamental change in ESD protection design, because it’s now reached the point where the limitations of traditional capacitance compensation techniques are too great. It’s led to the arrival of more advanced architectures that provide the signal integrity required by high-speed interfaces while simultaneously delivering the ESD protection necessary for reliable operation.
For more information, please visit http://www.onsemi.com.