Shown is a simplified continuous-time sigma-delta ADC model, comprising a sigma-delta modulator and a decimation filter.
The DT-S? input structure typically implements switched capacitors, and CT-S? ADCs use a continuous-time loop filter.
A comparison of discrete-time (DT loop filter) versus continuous-time (CT loop filter) modulator systems.
This second-order CT-S? ADC is shown with representative signal and noise transfer functions.
Sigma-delta converters are widely used today in applications demanding high precision and accuracy. A variant of the sigma-delta architecture, called the continuous-time sigma delta (CT-ΣΔ), has long been used in embedded applications, such as mobile handsets. Due to the high performance, efficiency, and ease of use of the CT-ΣΔ architecture, manufacturers of high-performance ADCs are now bringing this converter architecture to market as a standard product. This article will look at the CT-ΣΔ architecture and its associated advantages.
A simplified block diagram of a continuous-time sigma-delta ADC comprises a sigma-delta modulator and a decimation filter (Fig. 1). Much like the discrete-time sigmadelta converters found in a number of high-precision applications, the continuous-time sigma-delta architecture incorporates oversampling and noise shaping in order to achieve high resolution.
To understand how sigma-delta converters work, it’s important to briefly introduce the oversampling theory. Consider the technique of oversampling in the frequency domain, where a dc conversion has a quantisation error of up to 1/2 LSB. A perfect N-bit ADC has an rms quantisation noise of q/√12 uniformly distributed within the Nyquist band from dc to fS/2, where q is the value of an LSB and fS is the sample rate.
If the sample rate increases to kfS, the rms quantisation noise remains q/√12, but the noise is now distributed over a wider bandwidth from dc to kfS/2. The factor k is referred to as the oversampling ratio (OSR). Since the quantisation noise is distributed over a wider bandwidth, the noise within a narrow band of interest has been reduced by a factor of √k.
In combination with the principle of oversampling, a sigma-delta converter applies noise shaping in the modulator to further reduce the quantisation noise within the band of interest. Noise shaping, as the name implies, involves attenuating the in-band quantisation noise at the expense of amplifying noise in the out-of-band region. The resulting spectrum at the output has minimal quantisation noise in-band and large out-of-band noise (Fig. 1, again). If a digital low-pass filter is applied to the output, the out-ofband noise can be removed.
After filtering, the out-of-band region contains no quantisation noise or signal, allowing the output data rate to be reduced without corrupting the in-band signal. This process of filtering and samplingrate reduction is commonly referred to as decimation filtering. The decimation filter removes the large outof- band noise I; the result is a highperformance, wide-dynamic-range analog-to-digital converter.
DISCRETE-TIME VERSUS CONTINUOUS-TIME SIGMA-DELTA
Both discrete- and continuous-time sigma-delta ADCs share the same building blocks; the characteristics of the loop filter distinguishes one from the other. Discrete-time sigmadelta (DT-ΣΔ) ADCs use a discretetime loop filter, typically implemented with switched-capacitor circuits, whereas CT-ΣΔ ADCs use a continuous-time loop filter, which may be implemented with gm-C, active RC, LC, or other filtering elements (Fig. 2).
Figure 3 contrasts a system employing a DT modulator with one using a CT modulator. Both systems accept continuous-time analog inputs and produce discrete-time digital outputs. In the DT case, the modulator samples the input signal prior to the loop filter and the process of aliasing necessitates the need for an anti-alias filter (AAF). Furthermore, the DT modulator requires a driver circuit in order to isolate the continuous-time signal from the switched-capacitor input stage of the DT filter.
In the CT case, the continuoustime input may be applied directly to the CT filter without the need for an AAF or a driver. Although aliasing still occurs where sampling takes place, the sampling occurs at the same point where quantisation noise is injected into the loop for a CT system. Consequently, aliases are attenuated by a mechanism similar to the one that attenuates quantisation noise. This observation implies that any signal that would alias to the pass-band is attenuated by at least as much as the quantisation noise.
As an example, Figure 4 shows a second-order CT-ΣΔ ADC, and the representative quantisation noise and signal transfer functions (NTF and STF) that can be achieved with this structure. Note that since the NTF is a discrete-time transfer function, it’s only defined for frequencies from dc to fS/2, whereas the STF is a continuous-time function, and is defined for all frequencies.
For frequencies above fS/2, the STF represents the alias response of the system. Figure 4 shows that the STF has nulls at multiples of fS, i.e., at the location of the aliases. This alias protection is essentially “free” and substantial, even for such a low-order system. Higher-order systems or systems with a higher OSR can be expected to feature even greater alias protection. In essence, a CT-ΣΔ ADC can be considered a combination of an AAF and an ADC; this simplification results in lower system component count.
Another advantage of the CT approach relates to noise. Inside a DT loop filter, white noise aliases into the first Nyquist zone, whereas noise-aliasing only occurs at a noise-insensitive point in a CT loop filter. Consequently, CT-ΣΔ ADCs have the potential for lower noise at a given power than is possible with DT systems.
The preceding paragraphs described several ways in which CT-ΣΔ ADCs are superior to DT-ΣΔ ADCs. However, the CT approach isn’t without its drawbacks, including limited sample-rate range and a susceptibility to out-of-band signals.
SAMPLE-RATE RANGE
Since the loop-filter coefficients in a DT switched-capacitor loop filter are set by capacitor ratios, the clock rate of a DT-ΣΔ ADC is essentially arbitrary, up to some specified maximum. In a CT-ΣΔ ADC, however, the coefficients are related to the ratio of RC time-constants to the sampling period. To provide accurate loop-filter coefficients, CT-ΣΔ ADCs usually include programmable resistor/capacitor banks that are tuned to compensate for both process variation and the sampling rate. The limited tuning range of these banks translates into a limited range of sampling rates.
OUT-OF-BAND- SIGNAL HANDLING
The second issue concerning CT-ΣΔ ADCs relates to out-of-band signal handling. Two major topologies are used in ΣΔ ADCs: the socalled feed-forward and feedback architectures. Feed-forward architectures are more efficient (higher SNR for a given bandwidth and power) than feedback ADCs. However, continuous-time feed-forward architectures typically have an STF that doesn’t roll off at high frequencies and usually contains out-of-band peaks. Since these STF peaks are typically one or two octaves beyond the pass-band edge, they aren’t problematic in applications where the bulk of the signal energy is in or near the pass-band.
But, in communications applications with large far-out interferers, it’s necessary to either add a filter to attenuate these signals or allocate some of the ADC dynamic range to accommodate them. In contrast, feedback ADCs have STFs that roll off beyond the pass band and can thus accommodate far-out interfering signals that are actually above the converter’s full-scale.
NYQUIST VS. CT-ΣΔ
Similar to DT-ΣΔ converters, the Nyquist converter architecture utilises discrete-time circuits. Therefore, both architectures have similar input structures and driveramplifier requirements. The input structure of the Nyquist converter is a time-varying load because of the switched-capacitor input; therefore, the challenge becomes interfacing to a high capacitance input.
One solution is to use a differential driver amplifier that has sufficient linearity and drive strength. It’s important to pay careful attention to the common-mode levels between the driver amplifier and the ADC. In addition, the amplifier’s linearity must be optimised so as not to be the limiting factor in the system.
A common side effect of switchedcap inputs is the switching noise or kick-back associated with the sample-and-hold process. For this reason, external filtering plays an important role in removing unwanted switching noise. In addition to filtering the switching noise at the input, an anti-aliasing filter is required to attenuate the aliases due to the sampling process. Further, the need for alias protection in Nyquist ADCs often requires one or two octaves for a transition band, thus reducing the usable bandwidth to between 25% and 50% of the available bandwidth.
The combination of filtering and driver amplifier requirements of Nyquist converters typically increases design time, board space on the printed-circuit board, power consumption, noise, and distortion. However, one of the main advantages of Nyquist rate converters is that they can sample wider input bandwidth signals.
For example, a state-of-the-art commercial 16-bit sigma-delta ADC developed in 2008 has a bandwidth of 10 MHz, whereas a similarly advanced16-bit Nyquist ADC can sample a 100MHz of bandwidth. These important criteria need to be considered when choosing an ADC architecture.
CT ΣΔ ADCs offer an attractive solution, since they have inherent anti-aliasing, reducing or eliminating the need for an anti-alias filter. CT-ΣΔ ADCs also have a benign resistive input impedance, eliminating the need for a driver amplifier. In addition, the high dynamic range and superior noise performance that can be achieved using CT-ΣΔ ADCs can relax the gain requirements of signal chain components in many systems.
Utilising this innovative converter architecture, 16bit CT-ΣΔ ADCs such as the AD926x family from Analog Devices offer 86dB dynamic range over a 10MHz bandwidth with a programmable output data rate of 30Msamples/s to 160Msample/s.
This performance, coupled with the unique attributes of the CT-ΣΔ architecture, significantly simplifies system level design and helps reduce the cost, size, power consumption, and time-to-market of the end product.