When implementing logic functions, designers usually must trade off speed to attain low power consumption. With Lattice Semiconductor's ispMACH4000Z series of programmable logic devices (PLDs), designers can get high-speed PLDs that drop static power consumption to just 20 µA, worst case, for a 32-macrocell chip. In past portable-system designs, PLDs weren't very popular since they had standby power levels that drained the batteries too quickly. Additionally, PLDs typically aren't the lowest-cost option.
The lower power consumption of the 4000Z series lets portable systems last longer without sacrificing performance. The 32-macrocell ispMACH4032Z has a pin-to-pin propagation delay of just 3.5 ns, a clock-to-output delay of 3 ns, a setup time of just 2.2 ns, and a top operating frequency of 265 MHz. The 4000Z family includes two additional members, the 4064Z and 4128Z, which provide 64 and 128 macrocells, respectively.
All 4000Z devices can operate with a 1.8-V supply, but they can also run with voltages as low as 1.5 V. Each device has two I/O banks, and each bank has its own power-supply input. This allows designers to set the supply voltage at the desired level to support LVTTL or LVCMOS levels of 3.3, 2.5, or 1/8 V.
The 4032Z has 32 I/O pins and comes in a 49-contact chip-array BGA or a 48-lead TQFP. The 4064Z offers 32 or 64 I/O pins, and the 4128Z provides 64 or 92 I/O pins. In 100,000-unit lots, the 4032Z costs less than $1. Samples are immediately available. Lattice's ispLEVER suite of design tools supports all chips.