I2C Voltage Translation Buffer Caters To DDR4 Servers

I2C Voltage Translation Buffer Caters To DDR4 Servers

The Fast-mode Plus (Fm+) I²C-bus buffer is designed for emerging server applications that incorporate DDR4 SDRAM memory. NXP’s voltage-translating bus buffer—the company’s first Fm+ device specifically designed for servers—features voltage-level translation of 0.8 V (CPU) to 2.5 V (SDRAM module). The PCA9617A operates at up to 1 MHz with normal Fast-mode drive, enabling operation on more heavily capacitive loaded buses. However, it’s backward-compatible to Fast-mode and Standard-mode speeds. It retains all I²C-bus system operating modes and features during the level shifts. In addition, it permits extension of the I²C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines. The bus splits into two sections of 550 pF (max) at 1 MHz. The PCA9617A comes in TSSOP8 (MSOP8) “DP” and smaller leadless HWSON8 “TP” packages.

NXP

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