In digital, analog, and RF communications systems, jitter plays a large role in the degradation of signal integrity. This can include a reduced signal-to-noise ratio (SNR) or effective number of bits (ENOB) in analog-to-digital converters (ADCs) or increased bit error rate (BER) in digital and optical channels. Once you examine its sources, you can improve jitter performance from a systems perspective.
What Is Jitter?
In both analog and digital systems, clock sources are often designed to be very accurate and stable over time. In digital communications bit or symbol times, known as unit intervals (UIs), define the window that signifies the bit or symbol value. Any deviation from this timing may lead to errors and degrade the channel.
Jitter can affect both clock sources and digital communications by adding uncertainty to the expected time an edge (or symbol) should arrive. It also is cumulative and continues to increase as a signal propagates.
In sampled systems, such as ADCs used for digital signal processing, clock jitter adds noise and degrades the converter’s performance. In these applications, the better the jitter performance, the better the quality of the analog information being sampled.
Sources Of Jitter
There are two main categories of jitter: deterministic and random. Deterministic jitter is systemic and can be caused by a multitude of phenomena such as crosstalk, periodic noise such as the noise that comes from a switching power supply, and reflections. It is bounded (limited), and its sources are very well understood. Random jitter is unbounded and is caused by thermal or shot noise, as well as other random sources. Total system jitter is the sum of the deterministic and random jitter components. The farther from the source of a signal, the more jitter affects the quality.
Deterministic jitter can be broken into three major categories: periodic, data-dependent, and bounded-uncorrelated. Data-dependent jitter is further divided into duty cycle distortion and inter-symbol interference (ISI) (see the figure). Periodic jitter or sinusoidal jitter is caused by sources that repeat at a fixed frequency and magnitude. Switching power supplies and crosstalk are two major sources of this type of jitter. For example, placing a clock signal next to a data transmission line can significantly degrade the channel’s error rate.
Sometimes periodic jitter is intentional. A special type of periodic jitter called spread-spectrum clocking (SSC) is used to improve the electromagnetic interference (EMI) performance of computer interfaces such as PCI Express and Serial ATA. It is a form of frequency modulation (FM) imposed on the data clock and has the effect of spreading the radiated energy across a larger portion of the frequency spectrum. This lowers the power of any specific frequency and reduces the likelihood that the system will interfere with the operation of other equipment.
Crosstalk is another form of bounded jitter, but is uncorrelated to the actual signal since it comes from an adjacent channel. The adjoining channel is called the aggressor and bleeds some amount of its signal into the primary or victim channel, resulting in signal distortion. Crosstalk comes in two flavors: near-end crosstalk (NEXT) and far-end crosstalk (FEXT).
The near-end occurs when a driver of the aggressor channel is next to the receiver of the victim channel. Far-end crosstalk is the result of a driver at the end coupling with the receiver that is driven from the near end. Both types can reduce the SNR of the victim channel.
One solution that helps this type of jitter is to provide pre-emphasis (or de-emphasis) on the driver, rather than equalization at the receiver. This improves the SNR at the receiver and can help with the channel’s linear loss. Combined with careful layout, this approach helps mitigate crosstalk effects.
Data-dependent jitter has two main components: duty cycle distortion (DCD) and ISI. There are two primary causes of DCD jitter. If a transmitter is supplied theoretically perfect data (or a clock), and the transmitter’s threshold is offset from its ideal, then the output will have some amount of DCD as a function of the slew rate. The second component is caused by asymmetry in the driver’s rise and fall times. Both of these cause jitter at an ideal receiver given the variation in time the signal crosses the receiver’s switching threshold.
ISI jitter is caused by the history of information that precedes the current symbol or bit. It is the result of charging the transmission line and causing the ideal center point (or baseline) to move up and down. Also called baseline wander, it is run-length-dependent. Patterns with longer run lengths have more time to move the baseline. In a bandwidth-limited channel, pseudorandom binary sequences (PRBS) with longer run lengths have a higher ISI jitter than shorter patterns.
Poorly terminated transmission lines or discontinuities are another source of ISI reflections. The presence of impedance discontinuities reduces the channel bandwidth while the resultant reflections can affect timing, if they reach the receiver during an edge transition. This coincidence of the reflection and edge moves the signal slightly higher or lower, causing the receiver to transition at a slightly different time than expected. Discontinuities should be avoided and proper termination placed as close to the end of the transmission line as possible to reduce these effects.
As mentioned, several techniques are available to improve jitter performance. To reduce deterministic jitter, adding pre-emphasis (or de-emphasis) helps by improving the signal’s high-frequency content. The linear loss of a transmission line looks like a low-pass filter and, by increasing the high-frequency content, improves SNR. Coupled with linear equalization, this helps compensate for transmission line loss and further improves the channel. Careful layout, which should include minimizing discontinuities and placing termination of transmissions lines as close to the end as possible, can reduce the effects of deterministic jitter.
For random (unbounded) jitter, there comes a point where these techniques won’t provide enough compensation. The solution is re-clocking, which requires a phase-locking technique. This works for both clock sources and data sources. Once the signal passes the re-clocking circuitry, the random and deterministic jitter both are greatly reduced. Semiconductor devices are available for all of these functions with transmission speeds greater than 25 Gbits/s.
Jitter is ever present and has sources that range from systemic design issues to cosmic radiation and thermal noise. The issue is how well engineers deal with the problem. Careful layout, improving SNR through pre-emphasis, de-emphasis, and equalization, as well as the application of re-clocking devices can overcome even the nastiest jitter problems.