Electronic Design

Low-Dropout (LDO) Linear Regulators

Sponsored by Analog Devices Inc

What are the typical applications for a low-dropout (LDO) linear regulator?
LDO linear regulators usually are employed in systems that require a low-noise power source instead of a switching regulator that might upset the system. LDOs also find use in applications where the regulator must maintain regulation with small differences between the input supply voltage and output load voltage, such as battery-powered systems. Their low dropout voltage and low quiescent current make them a good fit for portable and wireless applications.

How much output current can an LDO provide?
LDOs with an on-chip power MOSFET or bipolar transistor typically provide outputs in the 50to 1000-mA range.

What is a typical LDO regulator circuit?
An LDO voltage regulator operates in the linear region with the topology shown in the figure. As a basic voltage regulator, its main components are a series pass transistor (bipolar transistor or MOSFET), differential error amplifier, and precise voltage reference.

What characteristics affect an LDO's performance?
The key operational factors for an LDO are its dropout voltage, power-supply rejection ratio, output noise, and quiescent current.

What is dropout voltage?
Low dropout refers to the difference between the input and output voltages that allow the IC to regulate the output load voltage. That is, an LDO can regulate the output load voltage until its input and output approach each other at the dropout voltage. Ideally, the dropout voltage should be as low as possible to minimize power dissipation and maximize efficiency. Typically, dropout is considered to be reached when the output voltage has dropped to 100 mV below its nominal value. The load current and pass transistor temperature affect the dropout voltage.

What is power-supply ripple rejection?
Power-supply ripple rejection (PSRR) affects the LDO's ability to prevent output voltage fluctuations caused by variations in input voltage. PSRR is usually specified at a specific frequency, for example, 60-dB rejection at 120 Hz. Low-ESR (equivalent series resistance) output capacitors and added reference voltage bypass capacitors improve the PSRR performance. Battery-based systems should employ LDOs that maintain high PSRR at low battery voltages.

What affects an LDO's output noise?
An LDO's internal voltage reference is a potential noise source, usually specified as microvolts rms over a specific bandwidth, such as 30 µV rms from 1 to 100 kHz. This low-level noise causes fewer problems than the switching transients and harmonics from a switch-mode converter. In the figure, the LDO has a (voltage-reference) bypass pin to filter reference voltage noise with a capacitor to ground. Adding the datasheet-specified input, output, and bypass capacitors usually results in a non-problematic noise level.

What is quiescent current?
Another important characteristic is the quiescent or ground current (the current flowing through the system when no load is present), which creates a difference between the input and output currents. The series pass element, topologies, and ambient temperature are the primary contributors to quiescent current. Quiescent current and input to output voltage limit LDO efficiency and should be minimized.

How does the output capacitor affect LDO performance?
Controlling the LDO's frequency compensation loop to include the load capacitor reduces sensitivity to the capacitor's ESR, which allows a stable LDO with good quality capacitors of any type. In addition, output capacitor placement should be as close as possible to the output.

What circuit features can enhance LDO performance?
An enable input permits external control of LDO turn-on and turn-off, which allow the sequencing of supplies in multirail systems. Soft-start limits inrush current and controls output voltage rise time during power-up. A sleep state minimizes power, particularly in battery-based systems. A bypass pin enables an external capacitor to reduce reference voltage noise. An error output indicates if the output is going out of regulation, also known as a voltage-good or power-good output. Thermal shutdown turns the LDO off if its temperature exceeds the specified amount. Overcurrent protection (OCP) limits the LDO's output current and power dissipation. And, another important feature available in the latest generation of LDOs is voltage tracking, which enables controlled sequencing of multiple LDOs powering multiple supply sensitive digital loads (e.g., an IC with an I/O and a core voltage requirement).

What factors determine the optimum LDO for a specific application?
Considerations include the type and range of the applied input voltage, required output voltage, maximum load current, minimum dropout voltage, quiescent current, power dissipation, and shutdown current.

How does output-capacitor ESR affect LDO performance?
The output capacitor's ESR can affect LDO control loop stability. For example, a minimum of 1µF capacitance with an ESR of 500 mW or less is usually recommended to ensure the stability of a CMOS LDO. Transient response to changes in load current is also affected by output capacitance. Plus, using a larger value of output capacitance improves the transient response of the LDO to large changes in load current.

What type of output capacitors should be employed with an LDO?
Any ceramic capacitors that are of good quality can be used with most LDOs, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics.

What is the effect of the input bypass capacitor?
Connecting a 1-µF capacitor from input to ground reduces the circuit sensitivity to printed-circuit-board (PCB) layout, especially when long input traces or high source impedances are encountered. If greater than 1 µF of output capacitance is required, the input capacitor should be increased to match it.

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