The move to bring broadband services capable of supporting the triple-play applications of voice, video, and data to first-mile customers (small businesses and the home) continues to evolve. A key player in this FTTx movement is GPON (Gigabit Passive Optical Network), a fiber-based network that provides a higher bandwidth alternative to existing solutions such as DSL and cable. FTTx refers to the family of first-mile applications, such as Fiber to the Home (FTTH), Fiber to the Building (FTTB), Fiber to the Curb (FTTC), etc.
With downstream data rates of up to 2.5 Gbits/s and the requirement to leverage the existing telecom infrastructure, GPON networks are proving to be a popular choice for these first-mile applications. Due to its increased bandwidth efficiency, forecasts show that GPON will overtake EPON (Ethernet Passive Optical Network) as the technology of choice for future first-mile networks.
GPON: A Functional View
Based on this reuse of existing infrastructure, GPON is a time-division-multiplexed (TDM) system. Here, end users are allocated time slots during which they can transmit their data from remote terminals. As shown in Figure 1, there are two main data flows in GPON. The downstream direction flows from the OLT (optical line terminal) to an optical splitter that broadcasts the data to multiple ONUs (optical network units). In the upstream direction, the process is reversed.
Each user (ONU) is assigned a time slot to transmit data, which is subsequently combined with other data on a single fiber and sent to the central office equipment (this is the OLT). Because ONUs are typically located apart from each other and ONU-sourced data consists of bursts, users will encounter inherent phase variations in the upstream data caused by different optical lengths of the multiple ONUs. The challenge for the OLT is to correctly “range” each ONU and successfully synchronize to every data burst at the upstream optical link.
At the OLT, lock-time requirements to handle these high-speed data bursts in the upstream traffic are very aggressive (typically 50 bit times for GPON), whereas traditional XAUI or SONET/SDH-based SERDES allow for much longer lock times (thousands of bit times). As a result, customers needed to use a specialized, discrete burst-mode receiver (BMR). However, traditional BMRs tend to expend a great deal of power and aren’t easily scalable, which can lead to a non-optimized footprint and, ultimately, additional system cost.
Until recently, there were no alternative solutions to these specialized BMRs. But with the advent of FPGAs that offer a fast-locking, low-latency, integrated BMR capability that supports up to 2-Gbit/s speeds, that is changing.
The Ideal BMR
As already noted, a BMR must satisfy a specialized set of requirements in order to handle the dynamic nature of upstream traffic. Ideally, the BMR must have very fast lock times and support high-speed serial data rates, while maintaining the smallest footprint with the least possible power consumption. Traditional BMRs have provided the data performance necessary for GPON, but there have been cost, power and board-space tradeoffs. On the other hand, FPGAs historically provided the flexibility and high level of integration required, but their SERDES haven’t been able to meet the lock times and data rates required by GPON.
The ideal solution would be the best of both the BMR and FPGA worlds. That solution is now at hand thanks to the I/O capabilities of today’s FPGAs. The unique ability of these programmable platforms to terminate upstream PON traffic on a per-pin basis provides a cost-effective and scalable solution when compared with traditional BMR devices.
The most common technique employed to date has been utilizing FPGA logic to oversample the incoming data. While successful, this approach has also been prone to performance and power concerns. An alternative approach to PON termination is offered by FPGAs such as the LatticeSC family. These devices incorporate specialized logic within each I/O cell that can dynamically adapt to differing line conditions without the use of FPGA logic.
Embedded within each I/O cell are an input delay block (INDEL) and adaptive input logic (AIL) that together dynamically compensate for timing/phase variations, allowing speeds of up to 2 Gbits/s per pin (Fig. 2). The end result is a complete I/O system that supports the fast lock times and performance of traditional BMRs but on a highly integrated, low-power programmable platform.
AIL Phase Correction
Traditional BMRs have employed clock data recovery (CDR) to generate the upstream sampling clock at the OLT. As mentioned previously, using this method of clocking for upstream GPON applications requires a very specialized, high-power circuit to meet the aggressive speed and lock-time demands of upstream traffic.
Since the physical layer of GPON is based on existing TDM infrastructure, GPON is by its nature “loop-timed,” which means the local reference clock at the OLT can serve as the reference clock to sample incoming data. The AIL takes advantage of this by generating a local 625-MHz clock from the local OLT clock source. This clock samples the incoming data that’s dynamically delayed on a burst-by-burst basis to compensate for the phase variations inherent to upstream traffic when terminating multiple ONUs.
The 128 tap delays (45 ps each) enable multiple, consecutive periods of input data to be available within the delay chain at any given time for sampling. The AIL monitors multiple samples of this input data and dynamically adjusts the clock/data-phase relationship until it finds a valid sample point. The input data signal is run through a delay chain with data, transitions, jitter, and noise all contained inside. The AIL then slides the acquisition window through the delay chain, searching for stable data based solely on data transitions. Once stable data is found, the AIL will continue to monitor the input and walk with the data, dynamically compensating for low-frequency jitter/wander and variations due to the effects of process, voltage, and temperature.
This novel approach of using a delay chain to create multiple copies of the data provides a lower-power solution than oversampling data with a higher speed clock. Figure 3 provides a high level view of the AIL methodology.
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The AIL window takes samples of data from the delay chain. The window contains edge-detection registers and a center-tap sampling register. This center-tap register is the actual register where the data is sampled and subsequently passed on to the FPGA fabric. The edge-detection registers serve as the “eyes and ears” of the window, as their feedback provides the information needed to drive the search algorithm. Up to four edge-detection registers are available on each side of the sampling register in the largest window size. Figure 4 shows a diagram of the register layout of the AIL window with the available window sizes.
The worst-case starting position for acquisition time is when the window is centered in a data transition. The window then begins searching for noise-free data by comparing data samples from the edge-detection and center-tap registers. Based on those values, the window will move continuously in a single direction in 90-ps steps until stable data is found. Once found, AIL continuously tracks the clock/data phase relationship, compensating for low-speed jitter/wander and other process, voltage and temperature changes. Figure 5 depicts an example of the search algorithm.
The window size is determined by calculating the worst-case data valid period (Fig. 6). The user selects the largest window possible that fits within this calculated worst-case window. For example, in an upstream GPON application, the data period is 800 ps. The GPON specification allows for .4UI of jitter, resulting in a data valid period of 480 ps (800 to 320 ps). Therefore, a 400-ps window size would be selected from the supplied GUI.
Once the window size is determined, window movement can now be considered. The worst-case scenario for the AIL in terms of acquisition is when it must overcome 160 ps of jitter, i.e. a starting point in the center of a transition (Fig. 7).
Based on 90-ps step sizes, it would take two delay steps (180 ps) for the center-tap register of the AIL to sample valid data, and four delay steps for the entire window to be in a noise-free environment. Remember that the user sees data from the center-tap register, so it’s not necessary for the entire window to be in the noise-free environment for the user to receive/detect valid data. Since the AIL needs four transitions per delay step, the user would see valid center-tap data after eight data transitions, while the whole window would be in a noise-free environment within 16 data transitions. Both are well within the GPON specification for initial data-acquisition times.
The AIL will continue to monitor and move the window as necessary based on data transitions. The algorithm and window design allow the AIL to tolerate high-frequency jitter and respond to low-frequency jitter by continuously monitoring the phase relationship and moving the window as necessary to maintain a noise-free environment.
Once the window finds a location free of data transitions, the edge-detection registers act as a buffer against high-frequency jitter. Figure 8 shows an occurrence of high-frequency jitter encroaching deep into the AIL window. If this transition is detected four consecutive times, the window will move. However, if this first transition is all that’s seen, it will be tolerated by the AIL because it’s not deep enough to impact the sampled data of the center-tap register in the middle of the window.
In the case of low-frequency jitter/wander, Figure 8 also shows how a phase shift over time is compensated for by the AIL. The built-in feature, which uses four edge detections before moving the window, allows the AIL to adjust slowly to low-frequency jitter (or wander). With this built-in hysteresis algorithm for data transitions, the AIL acts as a low-pass filter for the jitter/wander, allowing it to track variations due to the effects of process, voltage, and temperature changes.
The technological evolution that is bringing more bandwidth to first-mile customers has led to the rise in popularity of GPON technology. While viable solutions are available, the continued growth of the technology will depend on how quickly and cost-effectively future solutions can be realized. An integrated OLT receiver that provides the robust performance needed for a BMR, and does so in a single, scalable, small footprint package at half the power of existing solutions will undoubtedly accelerate the popularity of GPON technology.