Making the most of FUSI

July 5, 2006
The convergence of communications and computing on mobile devices, plus the rapid expansion of multimedia and gaming applications, has ensured that lower power consumption is the Holy Grail for semiconductor technology advancement.

An irrefutable constant in the design life of semiconductor companies is their relentless search for cost-effective ways to enhance device performance. As Texas Instruments correctly pointed out prior to the recent Symposium on VLSI Circuits, the convergence of communications and computing on mobile devices, plus the rapid expansion of multimedia and gaming applications, has ensured that lower power consumption is the Holy Grail for semiconductor technology advancement.

Not surprisingly, then, TI's 45nm process uses SmartReflex power and performance management technologies. They combine intelligent and adaptive silicon and circuit design that's aimed at tackling power-management challenges. Typically, TI takes a system-level approach with SmartReflex technologies to extend product capability across 45nm SoC design.

Interestingly, the VLSI Symposium highlighted a particular semiconductor technology that will undoubtedly help companies working in 45nm technology. IMEC, Europe's independent nanoelectronics and nanotechnology research institute, unveiled several breakthroughs on Ni-based FUSI (Full silicidation of polysilicon gates), making it a practical and reliable process for 45nm developments. Ultimately, FUSI will foster excellent low-power, high-performance specifications.

There's no doubt that FUSI, particularly a version using nickel, has become an attractive approach to integrating metallic gates into CMOS devices targeting low-power applications. Advantages include the compatibility with mainstream polysilicon front-end processing, nickel silicide's mid-gap work function, and the possibility of work function tuning via ion implantation. In addition, since the silicidation occurs at a relatively low temperature, it can be performed after junction activation.

However, some challenges remain with FUSI processing, including gaining full silicidation on all features and integrating FUSI with minimal impact to the CMOS process. But many semiconductor companies will say their greatest concern is scalability. We will see.

One thing is certain, though: Most leading companies are investigating the FUSI approach relative to 45nm processes as part of their pursuit for the Holy Grail of power efficiency.

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