Electronic Design

Making The Right MOSFET Moves

Hybrid technologies usually work well, providing they make the best of both the bipolar and MOSFET worlds, rather than magnify the worst. With this in mind, STMicroelectronics has developed a hybrid emitter-switched-bipolar transistor that the company says combines the strengths and eliminates the disadvantages of both technologies.

Power bipolar technology typically is used in switching applications at frequencies below 70 kHz. Its low collector-emitter saturation voltage brings the benefit of low conduction losses. But among its disadvantages are slow switching speeds, the need for high currents from driving circuitry, and problems related to fine-tuning this circuitry.

On the other hand, MOSFETs offer high switching speeds and need only very low current from the driving circuitry. Yet because of their cost, they take a larger bite out of the design budgets.

By combining these technologies, STMicro says its STE50DE100 reduces the conduction losses to the same level as those of a bipolar part (see the figure). All the while, it can switch at up to 150 kHz.

LOW-POWER SoC DESIGNS
The company also has been busy developing its 65-nm CMOS platform, which will help designers develop next-generation system-on-a-chip (SoC) products for low-power, wireless, and consumer applications. Each process option in the 65-nm library will shrink 90-nm products by half, improve speed by up to 30%, and reduce leakage, thereby cutting power consumption.

Development engineers at Royal Philips Electronics were also in a MOSFET mood, coming up with a line of n-channel devices based on mTrenchMOS technology. With a 9.3-mm2 footprint, they feature low on-resistance and are rated at 30 V, 20 V, and 12 V VDS. The mTrenchMOS products can be dropped into a range of applications as replacements for larger existing packages, or into new designs. Samples are available now.

Over in Germany, IXYS Corp. announced that its latest family of PolarHT Power MOSFETs has been designed into Samsung's Plasma Display Panels (PDPs). Included among these PDPs is the largest one ever built, a TV with a diagonal viewing dimension of 102 in. PolarHT MOSFETs can cope with plasma discharge, sustaining currents of up to 160 A.

TFE TRANSISTOR CONCEPT
Still in Germany, Infineon and the Technical University of Munich recently unveiled a scalable transistor concept. Now, complementary tunneling field-effect transistors (TFETs) can be fabricated in a standard silicon process with good performance for static and dynamic parameters. A low-power logic family based on the device exhibits the benefits with respect to extremely low power consumption and confirms compatibility with standard CMOS technology and circuit design.

"Quantum mechanical tunneling, up to now regarded as a parasitic effect, is utilized for the operation of this device," says Thomas Nirschl, an Infineon engineer and principal researcher on the TFET project.

What does it all mean? Short channel effects are universal in standard MOSFETs. They represent the gradual shorting of the source and drain diffusions as the gate length reduces to small values near to the depletion layer widths of source and drain. High doping of the channel region can suppress this effect, but at the expense of reduced electron mobility and lower speed.

To maintain gate control of short MOSFET channels, the gate dielectric's thickness also must be scaled down. But tunneling leakage through the conventional silicon dioxide means that new materials are required. Integrating these high-k dielectrics is a serious challenge for CMOS process technology.

A possible answer is the quantum-mechanical TFET, which provides an opportunity to scale down the geometries and reduce the supply voltages compared to standard MOSFETs. The TFET structure presented by Infineon and the Technical University of Munich features a tunnel junction at the source side of the channel. In the nonconducting TFETs, a large pn-diode barrier exists between source and drain, producing very low leakage currents. When a MOS channel is formed by forward-biasing the gate, a zener tunnel current evolves with a steep turn-on characteristic.

See associated figure

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