Get that edge in performance by taking advantage of surface-mount power devices. Historically, two factors have limited IMAX—the maximum sustainable current delivered by a power MOSFET: the channel on-resistance —RDS(on) due to I2R heating, and the mounted package's net thermal impedance. The latter determines the efficiency with which heat can flow from the die.
Computing a theoretical IMAX is relatively straightforward:
|IMAX = k √(||(TJ(MAX) - TA(MAX)||)|
is the sum of thermal impedances from junction to ambient; TJ(MAX) and TA(MAX) are the maximum allowable junction temperature and the maximum rated ambient temperature, respectively; and k is a data-sheet guard-band factor.
This is straightforward analysis, but it does ignore the packaging interconnect's resistance—on the order of milliohms—held (the channel resistance of leading power devices was a large fraction of an ohm). However, innovations in power-semiconductor fabrication processes and powerdevice designs have reduced RDS(on) to the order of milliohms as well, so power dissipation in the die no longer necessarily sets the upper current limit.
The distinction between older devices and modern power MOSFETs with ultra-low channel resistance is an important one. Understanding the mechanisms that set the current maximum gives insight into potential failure modes in devices that are subject to current overstress.
A LINK TO FUSING
Two types of current overstress in MOSFETs distinguish themselves by the durations over which they operate, as well as the failure modes to which they lead. Pulse-over-current conditions can ultimately result in fusing failures.
Metallic filaments analysed over durations significantly shorter than the thermal time constant of their surroundings generally follow an I2t fuse characteristic in vacuum or gas. That characteristic depends on the metallic's melting temperature, cross section, and resistivity. Fuse currents for metal wires embedded in solid materials, such as organic packaging compounds, shift depending on the thermal properties of the compound.
Improvements in process, device, and packaging technologies, coupled with the further miniaturisation of powerstage, circuit-board layouts enabled by those advances, reduce the total impedance in a current transient's path.
For traditional power packages, for instance the TO-220 and D2PAK, this means innovations that might increase the maximum sustainable current are likely to have little or no effect on the device's peak-pulse-current limit. In practice, the fusing-current limit of power-device bond wires and power-section pc-board traces set an application's peak-pulse-current limit.
The steady state
The continuous-current case doesn't yield to such simple analysis. Whereas, historically, I2R heating in the channel dominated the thermal system, such is no longer the case for modern devices. In these cases, the on-resistance, bond-wire resistance, and lead resistance measure to similar orders of magnitude. As a result, for these devices, the thermal properties of the MOSFET silicon and its packaging, interconnects, mounting method, and mounting substrate all contribute systemically.
A recent investigation into the thermal performance of advanced MOSFETs in TO-220 and D2PAK reveals details of the thermal system for mounted devices under steady-state currents (Fig. 1). A custom-made clamping heat-sink fixture provided multi-site temperature data from five thermocouples formed of 3-mil copper and wire. The thermocouples measured the temperature of the ambient surroundings, the heat sink immediately under the device, the bond wire through a small aperture etched into the sample's package, one of the MOSFET's current-carrying leads, and the pc board near the solder joints.
Peak temperature occurred at the lead, which though sensible in retrospect, was surprising upon initial discovery. With die, bond wire, and lead all contributing similar fractions to the total path resistance, the resulting temperature at each point is a strong function of the local thermal impedance as well as the temperature of adjacent areas.
The intimate contact and low thermal resistance between die and power tab, and between power tab and heat sink, provides an efficient heat-flow path away from the die. The bond wire benefits from the thermal conductivity of the organic packaging compound that surrounds it.
Though not as efficient as the die's path through the power tab, the packaging compound does facilitate heat flow better than the air—a reasonably good thermal insulator in itself—that is surrounding much of the lead (Fig. 2).
In addition, counter-intuitively, the data shows that a through-hole, lead-attach method allows for greater sustained currents than surface-mount lead attach for otherwise similar packages and heat-sinking methods.
Shortening the lead length from package exit to board termination reduces both the lead's contribution to the total path resistance and the thermal impedance to the pc-board copper plane. Experiments used both lead-attach methods with devices clamped to the heat sink shown in Figure 1. Device leads terminated on pc boards with 1-in.2 copper planes on both sides with vias connecting the layers.
With a 175—C maximum temperature as the cutoff criterion, through-hole-attached devices were able to operate with 8% greater steady-state currents than that of surface-mount-attached devices.
The advantage of surfacemount power devices is significant to OEM manufacturing flows, particularly for products that stress both high efficiency and high power density. In such cases, the thermal performance of packages such as the DirectFET can provide current-carrying capability superior to TO-220 and D2PAK packaged MOSFETs, and still maintain full compatibility with automated surface-mount-assembly processes.