Programmable-gain amplifiers (PGAs) are often used in communication systems, such as basestations. Designers can select fully integrated, single-IC PGAs, which are now available with bandwidths over 500 MHz. But obtaining the low second- and third-order distortion that is critical in communication applications isn't easily achieved.
Combine that with the desire for greater choice in the attenuation level and step size, and designers may opt to construct a PGA using a high-performance, fixed-gain amplifier with analog-switch and resistor ICs ahead of the amplifier. Alternatively, they may place an order for an ASIC based on the catalog part.
The dynamic performance of a PGA depends primarily on the characteristics of the amplifier, which should have a high input impedance. But if the switch array and layout aren't optimal, the performance of the PGA can be ruined. An Idea For Design from several years ago ("Programmable-Gain Amp Uses Arbitrary-Attenuation Step Ladder,") employs an R-2R ladder and switches tapping off of each ladder node. The switch outputs are tied together and fed into an amplifier. Figure 1 shows a similar arrangement. This article describes how to improve on that circuit.
The large number of switches adds distortion from switch parasitic capacitance and crosstalk coupling. It also reduces the bandwidth of the signal path. The magnitude of the parasitic capacitance varies with signal amplitude and operating conditions. Therefore, different portions of the signal are transmitted in a different, nonlinear way, which causes the distortion. The on resistance of the switches is also nonlinear, adding to distortion. Either MOSFET or bipolar switches may be used.
To reduce power consumption and the asymmetries produced by thermal gradients, MOS switches (ICs or transistors) may be better. The techniques discussed here to improve PGA performance apply to either technology. Also, you can apply them to single-ended or differential versions of PGAs.
One way to reduce capacitive parasitics and nonlinearity is to cascade the switches, creating a first bank with a larger number of switches feeding a second bank with fewer switches. This reduces the nonlinearities at the output, where the switches feed the amplifier's input. An added benefit is easier circuit layout and equalization of the path lengths (Fig. 2). To simplify the decoding logic enabling a switch, the number of switches should be selected based on a binary choice. (The logic controlling each switch isn't shown.) Cascading yet more switch banks increases the on resistance serially and should be avoided.
If the switch array is at the transistor level, there will be an optimal switch size (that is, W/L ratio) that will provide the least distortion. The first bank may be NMOS switches and the second bank PMOS switches to achieve an overall signal path on resistance that's flat with respect to voltage. For speed, they may be all NMOS. Each switch should be laid out together with its corresponding resistors in the R-2R ladder, forming a unit cell.
The entire set of unit cells for the first bank should be laid out, say, clockwise. For example, if it's two rows, start the input at the center (thermal centerline) of the bottom row, and go clockwise. Then the last unit cell will be adjacent to the first input unit cell, but with a ground line shield separating the two. This arrangement reduces asymmetries due to gradients. Care must be taken to avoid coupling input signals with different delays directly to the next bank and to the amplifier's nodes.
Another problem is that when switches are turned off (the units that aren't selected to be on), the voltage drifts on their inputs. Therefore, turning on those switches starts them at an unknown voltage, creating input-voltage-dependent nonlinearities. As a result, a reference voltage is selectively provided to the inputs of the switches to start the voltage swing at a known baseline voltage (Fig. 3).