Electronic Design
Peak Current Mode Control Will Never Die!??

Peak Current Mode Control Will Never Die!??

As a youngster, I watched Dee Snider of the rock band Twisted Sister battle over the censorship of rock and roll with Tipper Gore and the Parents Music Resource Center. Being somewhat concerned for the future of rock and roll, I took solace in some words from Brian Johnson of AC/DC: “Rock and roll ain’t noise pollution…. Rock and roll will never die.”

As a distant parallel to this, with more and more digital controls entering the switched-mode power-supply (SMPS) control market, there are more and more skeptics when it comes to the future of peak current-mode control (CMC). I wonder if peak CMC will survive like rock and roll did.

Where Did Peak CMC Come From?

Originally, Cecil Deisch invented peak CMC at Bell Labs/Western Electric to balance the flux in the transformer in a push-pull converter and keep the core from walking off into saturation from a minor volt*time product difference caused by slightly asymmetric drive waveforms and/or load transients.

The solution was proven by placing a couple of fast PN junctions in series with the drain or collector of a switch on one leg, forcing a substantial volt*time imbalance. Peak CMC would terminate the pulses on the unburdened leg early, keeping the flux balanced and allowing the converter to run and transfer power to the load. Prior to this, there was no similar correction mechanism.  

How Does It Work?

It’s old hat for a lot of us, but I haven’t seen a practical explanation of peak CMC for quite some time. Peak CMC places a fast current loop inside the voltage control loop. This loop senses the inductor current and uses this information as the ramp signal to the pulse-width modulation (PWM) comparator. This loop can interrupt the drive to the output devices in the propagation delay time of the pulse-width modulator and driver when a fault is detected. Figure 1 depicts peak CMC in a buck converter.

But the real beauty of the topology lies in the transfer function of the converter. Since peak CMC uses the output current as the ramp to the PWM comparator, the output inductor effectively drops out of the transfer function of the converter at most any condition with output current. This then makes the double pole at the resonant frequency of the output inductor and output capacitor bank look like a single pole.

A single pole operates with less phase/time lag, so a converter with peak CMC will have better transient response than a converter with voltage-mode PWM control. However, there are places where this isn’t true, namely the multiphase processor power world, where add-ons to the voltage-mode control loop turn on all phases when a transient high current load transient is detected. 

The other advantage of having this fast inside loop is that of a feedforward. This is not entirely obvious. Consider the output inductor current waveform for a few cycles when the line voltage is increasing. Initially, the slope of the inductor current is at some nominal value. But as line increases, the secondary voltage increases. The output hasn’t changed, so the slope of the current waveform has to get steeper (recall: V = –Ldi/dt). This steeper current waveform will terminate the cycle more quickly, reducing the duty cycle. Consequently, it acts as a fast feedforward.

This can be seen in Figure 2, which shows us the waveforms from the converter and peak CMC control in Figure 1. The slope changes instantaneously as the voltage excitation changes—nearly an instantaneous feedforward in situ. By comparison, in a voltage-mode controller, we would wait for the line transient to raise the output voltage slightly. Then, the voltage-mode controller would fold back the duty cycle of the PWM output after some PID loop time constant.

Caveats Of Peak CMC

There are places where peak CMC won’t work without additional circuitry. Let’s consider an offline half bridge converter with a mild overcurrent event or asymetry in the secondary (depicted with the extra diodes in Figure 3). This will cause a primary switch to turn off early, creating an increasing charge imbalance in the decoupling capacitors that maintain the return voltage at VCC/2.

This charge imbalance shows up as a voltage difference at the midpoint so the midpoint voltage is no longer equal to VCC/2. The very next cycle will see a lower capacitor voltage in its respective loop, so the current will take longer to ramp up to the shutdown value at the comparator. The next cycle will see an even larger imbalance in the midpoint voltage and deliver a much higher voltage to the primary. As a result, the pulse will terminate much earlier due to the larger slope of the current ramp. The next pulse will see an even lower voltage and take even longer to terminate. You get the idea.

The charge imbalance in the capacitors caused by the first asymmetrical interrupt caused by peak CMC builds on a cycle by cycle basis. The end result of this is a midpoint voltage that is shifted to either VCC or ground and possibly a saturated transformer, even though the peak CMC mechanism tried to correct the condition. There are methods to get around this, such as setting up a pulse-width control circuit to maintain the charge (and VCC/2) balance in the decoupling caps.  

In a peak CMC power factor correction (PFC) circuit, there is a little excessive distortion in the line current waveform due to a slight offset caused by the peak CMC comparator. This needs a little explanation. At the minima of the rectified ac line input, the duty cycle of the PFC is at or near its maximum. The on time is very large, and the off time is very small. This occurs on both sides of a half wave of the ac sine.

This serves to retard the current waveform slightly with respect to the voltage waveform. The power factor can’t be optimal, but it can still be quite good. This is considered as a slight phase delay, with a worst case time value of 1/fsw. If we rationalize this against the period of an ac line cycle, it is a very minimal phase delay, less than 0.12% or 0.43° for a 100-kHz PFC stage and 60-Hz line frequency. In most cases this isn’t a problem, but worthy of mentioning. Average CMC resolves this issue (Fig. 4).    

In the academic world, we are taught that slope compensation is required for duty cycles beyond 50%. This is easily proven. With a buck converter as the vehicle, we can set up a converter where the input is 10 V, the output is 7.5 V, and the load current is substantial with only the output current as the ramp signal at the comparator. Under these conditions, the inductor current is clearly in continuous conduction mode.

Let’s then have a load transient that causes the peak CMC loop to interrupt the drive to the high-side switch slightly early. Note that there is a very short time for the inductor current to decay and the flux in the inductor core to reset itself. The load voltage determines the falling slope of the inductor. As long as the load isn’t shorted, the current in the output inductor will take a long time to ramp down to the lower threshold value at the PWM comparator. 

When the clock initiates the next cycle, the switch never turns on, because the current is still too high (or it turns on very briefly at the minimum duty cycle of the controller). If the current is really high, the next cycle may see the same conditions and remain effectively off. This condition will make the converter oscillate at some subharmonic of the switching frequency of the clock of the PWM.

Slope compensation cures this by introducing a means to bring the ramp down to zero during the short deadtime. The ramp of the internal clock signal is summed with the sensed current waveform. There will still be very short pulses for overcurrent conditions, but by summing the clock signal in with the current signal we have created a means to resolve this subharmonic oscillation. In applications, I’ve found it easier to use slope compensation for most any duty cycle in peak CMC operation simply due to noise on the current waveform and the high bandwidth of the comparator that sees this signal. 

“My DSP engineers will emulate that simple stuff in two hours!”

A DSP expert once told me that peak CMC was easy to emulate and that he’d have a working solution that behaved just like peak CMC in “two hours.” Five years later, he had something that remotely resembled peak CMC working at a distance at a trade show. It couldn’t handle a short circuit and had no feedforward. He also mentioned that analog control was completely dead and no longer needed. But I didn’t have decades to wait and see how he’d obsolete analog control with another “two-hour fix.”

Hot air notwithstanding, there have been some wonderful breakthroughs in the digital control of power supplies. The multiphase-processor power arena continues to see incredible features well beyond margining a trim digital-to-analog converter (DAC) with VID codes.

What Does It Cost?

In most designs, it gets down to dollars and cents. If I open the Digi-Key catalog and compare the UC3842 varieties against small microprocessors at similar volumes, the peak CMC IC comes in cheaper. Yes, the microprocessor or DSP can add in more features. Slope compensation and poles, zeros, and gains in the control loop can be parametrics in a GUI. Margining can also be programmed, as can min and max duty cycles, health monitoring, reporting, etc. These are great features that many high-end power-supply designers are considering.

But when it gets down to pinching pennies, perhaps in a silver box, a lighting ballast, a bias supply, or a cost-sensitive charger, peak CMC maintain its foothold. In terms of silicon real estate, a high-speed comparator, error amp, and bandgap require a lot less space than comparable processing and logic cells. Silicon real estate has been shown to correlate well to price, so the smaller peak CMC control die area is cheaper.

The Future Of Peak CMC

If I put on my marketing cap, I’ve seen the UC3842 controller, the basis of most any peak CMC design, cloned by more vendors than an LM2902 quad op amp or the TL431 reference. I’ve seen improvements to the IC that took it into a lower bias current biCMOS design process. Every other SMPS that I’ve benchmarked had a UC3842 in it somewhere. Peak CMC is far from gone.

The future of peak CMC will be exciting. We will likely see an ingress of digital features to the peak CMC architecture and true mixed-mode IC design features. The digital designers will realize that a fast comparator is easier if left as a fast comparator and not emulated. The analog designers will take advantage of trim DACs, reporting, and perhaps a GUI to program poles and zeros in the control loop. The result will be a great controller with a lot of cool features once everyone’s pride heals up and the marketing entropy subsides.


Hopefully I’ve provided a reasonable understanding of peak CMC and it’s origins, uses, and caveats. It’s a longtime favorite control method of mine, and I’ve found that the knowledge is scattered at best. Having spent a lot of time designing SMPSs, I believe peak CMC will survive just as hearty as the wailings of Brian Johnson and his predecessor Bon Scott, because it too “makes good good sense” whether in terms of the performance or cost. The leading controller ICs will ultimately incorporate digital features and perhaps a GUI, but there’s no simple microcode substitute for peak CMC.


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