Electronic Design

Power amplifier buffer features digital bias adjustment

The day may be near when every amplifier application can be served simply by finding the right off-the-shelf standalone chip. Maybe. But for now, many jobs require that even the best monolithic devices be supplemented with a sprinkling of active discrete devices. One such category of application is the high-output-current, high-frequency buffer amplifier.

Of course it’s simplicity in itself to add an arbitrary amount of muscle to a “milquetoast” op amp by following it with a class AB complementary bipolar emitter-follower or FET source follower pair like Q1 and Q2 in the figure. Many successful driver designs are based on just this elementary topology. But all such designs must confront the problem of stable dc biasing of the follower while avoiding unconscionable amounts of quiescent power draw and unbearable levels of harmonic distortion. This is a problem fraught with the classic twin-design-bogeymen of thermal runaway and crossover distortion.

The new solution to this old puzzle described here comprises an automatic bias adjustment loop consisting of a Xicor digital potentiometer P1, International Rectifier photovoltaic optoisolator O1, CMOS switches S1-S3, and Linear Technology op amps A2-3. The resulting adjustment loop includes two modes of operation selected by the CMOS/TTL-compatible ADJ input.

When ADJ = 0, S3 closes a normal feedback loop around A1 and the Q1/Q2 pair thus forcing the circuit to become a fairly normal, gain of -5 amplifier with a bandpass of dc to 10 MHz, full power bandwidth (limited by A1 slew) of 5 MHz, and output limits of ±10 V and ±10 A. Harmonic distortion over the full operating range is minimized by the impressive GBW of capacitive-load-compatible A1 combined with stable quiescent biasing of the Q1/Q2 pair to a thrifty no-signal value of 50 mA. The trick behind these performance numbers is the way an appropriate bias level for the follower is achieved, one that’s independent of temperature and component tolerance variations.

To understand how this is done, consider how the circuit rearranges itself when ADJ =1 causes S3 to disconnect A1’s input from the signal source and substitute a ground reference. Simultaneously, the S1/S2, 20-Hz multivibrator is enabled and begins clocking P1. In response, P1 begins to vary the input to A3, which then servos the control current into O1 and thus the net gate bias voltage at the follower MOSFETs.

This action combines with A2 to establish a feedback loop, which tends to drive the follower pair to the desired zero-signal bias. This action occurs because, if the follower bias current IQ is less than 50 mA, then the drop across R3 will be less than the drop across R4. As a result, A2 drives the Up/Down input of P1 high (Up). Therefore, on the next negative transition of the clock, the VW terminal of P1 will make one step toward the VH terminal. This increases the drive to C1, which ups the follower bias.

If IQ is more than 50 mA, then A2’s output state will reverse, causing P1 to step VW toward VL and decrease the follower quiescent bias. Consequently, after a maximum of 5 seconds and 99 multivibrator cycles, the follower bias will have been forced to converge to the bias level set by the R4/R3 ratio. ADJ then may be reset to zero for normal amplifier operation; the final bias setting will be retained by P1 until either power is removed or a new ADJ cycle initiated. Thermal coupling between D1/Q1 and D2/Q2 improves overall bias stability between adjustment cycles.

Although illustrated with ±15-V supplies, the unique “Over-The-Top” input topology of A2 is compatible with V+ voltages as high as 36 V (but be careful to observe A1 limitations). Also, there is no requirement that the V+ and V− voltages be symmetrical. Many variations are possible when selecting A1 and the follower MOSFETs to achieve different combinations of output capabilities.

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