Electronic Design

Power And Thermal Analysis Are Best Done Together

Advanced power-reduction techniques, such as multi-VDD architectures and power-aware clock tree synthesis (CTS), allow designers to implement large, complex SoCs that consume less power. Leakage power can be minimized by using multi-threshold libraries and by shutting off blocks based on the mode of operation. Dynamic power can also be reduced using different blocks operating at varying voltages. Significant power savings can be achieved through power-aware CTS techniques, such as clock-gate cloning and un-cloning, clustering of flops, activity-driven global placement, and optimal buffer insertion.

For more accurate power reduction, the power-analysis engine should be equipped with full-chip thermal-analysis capability. Device temperature significantly impacts the sub-threshold leakage and transition times. Chip power consumption is translated to the rise of device temperatures and interconnects above ambient temperature. Use of power-reduction techniques and different activity profiles of blocks result in a non-uniform thermal profile over the die.

Using a uniform temperature for all devices either at best- or worst-case corners results in major power-estimation errors. Having the accurate device temperature map is necessary for more accurate power analysis, which leads to a more accurate thermal profile. This highlights the need for self-consistent power and thermal analysis during the design flow (see the figure).

Evaluation of different design tradeoffs is crucial toward achieving an optimal design from combined power and thermal point of views. While, for example, power-driven clustering of sequential elements along with the activity-driven placement result in reduced high-activity wire lengths and dynamic power, it eventually creates new hotspots by forcing higher power cells to be in closer proximities. The increased temperature of these cells increases their leakage power. Only by deploying a combined thermally aware power-reduction approach during the clustering could the power-optimal location of the cells be found.

Simultaneous power and thermal analysis is essential for evaluation of the power-optimization goals, adjusting the design margins, and selection of the most cost-effective package and cooling solutions.

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