Cambridge, England and San Francisco, Calif., USA:
A design collaboration between the Taiwan Semiconductor Manufacturing Company (TSMC) and ARM on a 65nm low-power test chip resulted in significantly reduced dynamic and leakage power performance, claim the companies.
The 65nm test chip, based on the ARM926EJ-S processor, demonstrated advanced power-management characteristics. By applying dynamic voltage and frequency scaling techniques, the test chip will operate at very low power levels for each mode of operation. In this case, the ARM test chip achieved a dynamic power reduction of over 50%, claim the collaborators. Significantly, even on this TSMC 65LP low-leakage process, advanced power-gating technology further reduced standby leakage by a factor of eight.
"One of TSMC's key differentiators is our insistence on proving our services, and those of our partners, in silicon before bringing them to the design community," says Ed Wan, senior director of design services product marketing.
"Power efficiency is the most important challenge facing the semiconductor industry as mobile devices exploit advanced processes to deliver greater functionality and performance," adds David Flynn, ARM Fellow. "ARM and TSMC are partnering on 65nm and 45nm technology development, and this project demonstrates the significant leakage and dynamic power reductions that we can achieve through close technical collaboration and implementation of fully functional silicon."
The test chip incorporates low-power memory macros, level shifters, retention flip-flops, and isolation cells in the library, which is characterised for multiple voltages.