Electronic Design

Power Supply Cuts Switching Noise In DDR Memory Systems

This design idea describes a unique, low-cost power-supply circuit for a double-data-rate (DDR) memory system. Conventional designs for DDR memories consist of a dual buck converter and a voltage reference. In contrast, this design replaces one buck converter with a linear regulator (Fig. 1). The benefit of this approach is replacing the relatively large inductor and associated switching noise of a pulse-width modulated (PWM) converter with a small, low-noise op-amp linear regulator.

DDR memories bring new challenges to the power-supply designer. They require an efficient main power source of 2.5 V (VDD) and a termination voltage (VTT) that accurately tracks one-half of VDD (i.e., 1.25 V) and can both source and sink current. A third voltage is needed (VREF) to track VDD/2.

In this circuit, a low-voltage synchronous buck converter generates an 8-A VDD output at 2.5 V. The VTT and VREF voltages are produced with an op-amp linear-regulator design. The circuit is designed for low-power DDR systems, like desktop PCs. But its output power can be increased by selecting the proper external inductor and capacitors for high-power systems like PC workstations.

Voltage VDD powers the memory ICs and the buffer interface circuits. VTT is used for the pull-up resistors and must be able to either sink or source current. To save power, VTT is equal to VDD/2 instead of VDD. The power dissipated in the resistors equals the voltage squared divided by the bus resistance. So a termination voltage of VDD/2 yields a factor-of-four power savings. The third voltage is implemented as a reference voltage to the differential-amplifier input section of the receiver ICs.

The 2.5-V VDD supply uses an ON Semiconductor NCP1571 low-voltage synchronous buck controller. The controller contains the required circuitry for a synchronous N-channel MOSFET buck regulator with a 200-ns transient response, an output regulation of ±1%, and a fixed internal frequency of 200 kHz.

As mentioned, the VTT supply is the same as one-half of the VDD voltage, or approximately 1.25 V. Op amps U2a and U2b function as voltage followers to create VTT. The input to U2b comes from the resistive voltage divider formed by R5 and R6. This splits the 2.5-V VDD supply in two to form the VREF reference voltage. Also, U2b provides filtering to remove any high-frequency switching noise produced by the synchronous buck converter. The VTT output—formed by U2a and transistors Q3 and Q4—tracks the voltage at the noninverting terminal by virtue of its voltage-follower circuit configuration. Thus, the VTT supply's output voltage is referenced to 50% of the 2.5-V VDD supply, rather than an absolute 1.25-V reference.

The sink and source feature of the VTT supply is provided by MOSFETs Q3 and Q4, which extend the current capacity of the basic op-amp circuit. When the VTT supply is in the current-sinking mode, Q3 is "OFF" while Q4 is "ON." The output of U2a will be at a negative voltage to control the VGS of the P-channel MOSFET (Q4) to maintain the VTT voltage of 1.25 V.

In a similar manner, when the VTT supply is sourcing current, Q3 is "ON" and Q4 is "OFF." The output of U2a will reach a positive voltage to control the VGS of the N-channel MOSFET (Q3) to maintain the 1.25-V VTT. Resistor R7 isolates the output of U2b from VTT and the bulk capacitor, C15. In addition, R7 provides negative feedback to reduce the output resistance of the VTT circuit.

VDD, VTT, and VREF were measured at 2.458 V ±0.015 V, 1.224 V ±0.008 V, and 1.225 V ±0.008 V, respectively. The load range was no load to 8 A for VDD, and ±2 A for VTT. The efficiency is about 80% for a VDD current load greater than 2 A (Fig. 2). Figure 3 shows the steady-state VDD and VTT ripple voltages.

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