Switched-capacitor blocks are easily configured to be integrators. When configured as an integrator, a switch-capacitor block can function as an op amp. Closed-loop stability is achieved by parametrizing the capacitor values and sample frequency, which allow for precise gain-bandwidth control. Adding an external pass transistor and current-setting resistor enables easy construction of a programmable current source.
Figure 1 shows a classic current source built with an op amp and a bipolar pass transistor. This circuit has an op amp configured with negative feedback. The op amp tries everything to make the voltage difference between its inputs zero. This condition is met when the op amp's output is a base-emitter junction potential above VSET.
The voltage across the reference resistor is one base-emitter junction potential, VBE (about 0.7 V for silicon transistors), lower than the op-amp output or VSET. The load current approximately equals the set current. It differs by the beta value of the transistor.
A generic compensated op amp has an open-loop dc gain and rolls off at the roll-off frequency, gain/GBW. The frequency where the gain = 1 is known as the gain-bandwidth (GBW). For frequencies greater than the roll-off point, this transfer function approximates an integrator. So for closed-loop control circuits, an integrator can be used in lieu of an op amp. The switched-capacitor integrator in Figure 2 has a gain bandwidth of:
GBW = (fs/2p)(CB/CF)(1)
The switches are manipulated to transfer charge from the input to the feedback capacitor. The rate of this transfer is known as the sampling frequency, fS. Changing the values of CB, CF, or fS alters the gain-bandwidth. Flexible control of GBW lets users design a stable, closed-loop feedback system.
Figure 3 shows a modified differential-input integrator. The integrator's output is connected to an analog buffer and brought out to a pin. This analog output is fed back to a pin having a negative (CB) input to the integrator. Because this transfer equation is that of a single-pole, low-pass filter with gain, the gain is:
Gain = CA/CB(2)
The gain of the CB path is always negative. ASIGN controls the CA path gain's polarity.
To make a current source, a bipolar transistor is added to the output of the differential integrator. The transistor's emitter is fed back to the negative input. The CA input connects to a reference voltage, VREF. Because of the negative feedback, the integrator's output will do what is necessary to satisfy Equation 3 in the design example discussed below. The resistor at the emitter converts this voltage to a current. This current flows through the collector to the load.
Consider the following design example. To create a 500-mA current source, a 1-O resistor is placed in series with the base of the transistor. The resistor is referenced to ground (GND), while the integrator is biased to some artificial ground, AGND. Several system parameters must be set: AGND is set to 1.3 V above GND, VREF is set to 1.3 V above AGND, and fS is set to 250 kHz.
During operation, VE must be 0.5 V above GND (0.8 V below AGND). The resistor will dissipate 0.25 W at this voltage. A 0.5-O resistor is selected. Again, due to negative feedback, the integrator causes Equation 3 to be satisfied.
ASIGNVREFCA = VECA(3)
ASIGN(CA/CB) = VE/VREF = —0.8 V/1.3 V
One solution is:
CA = 16, CB = 26, ASIGN = Neg
Note that there are no units for the capacitors. The ratio of the capacitors, not their actual values, is important. For an integrator built with a switched-capacitor block on Cypress MicroSystem's programmable system on a chip, PSoC, the CA and CB capacitors can be programmed from 0 to 31 units, and the CF capacitor can be set to either 16 or 32 units. A unit of capacitance is about 50 fF.
Setting CF to 32 and applying these parameters to Equation 1 results in the gain-bandwidth value:
GBW = (fs/2p)(CB/CF)
= (250 kHz/2p)(26/32)
= 32.3 kHz
For a dc current source, a 32-kHz gain-bandwidth allows for fast response to load changes. If a component with high phase shift is added to the feedback loop, the question of stability arises. Will this circuit be stable? If the phase shift is excessive, the gain bandwidth can be made smaller to ensure system stability.