Pressure is mounting to squeeze more power out of cell-phone and portable-appliance batteries. Power-MOSFET suppliers are tapping every trick they can to boost performance. One company, Intersil Corp. of Palm Bay, Fla., has enhanced its trench process to obtain remarkably higher power efficiency from its transistors. By increasing the channel density within the switching device's cell structure, Intersil's DenseTrench process substantially cuts the MOSFET's on-resistance without degrading the gate charge.
Due to the flexibility of the process, only minor modifications are needed to optimize the on-resistance and gate-charge tradeoff. According to Christopher L. Rexer, manager for low-voltage power MOSFET development at Intersil, "Unclamped inductive switching capability is also addressed by the flexibility afforded by the DenseTrench technology. In short, this flexibility will deliver market-specific MOSFETs."
Designers incorporated an improved self-alignment technique to closely pack transistors using stripe geometry (see the figure). As a result, Rexer claims, DenseTrench offers over 150 m/cm2 of channel density—twice the total of earlier trench-based MOSFETs. Coupled with this density, the stripe geometry ensures optimal tuning of the epitaxial area for lowering the resistance. That translates into lower specific resistance, which in turn cuts the MOSFET's RDS(ON). The specific resistance reported for a 30-V n-channel DenseTrench MOSFET is 0.18 mΩ/cm2.
Though the initial six MOSFETs are 30-V n-channel devices that come in a variety of packages, Intersil plans to extend the DenseTrench capability across the 20- to 200-V range for both n- and p-channel parts. At VGS =10 V, the maximum RDS(ON) ranges from 4.9 mΩ in an SO-8 package to 16 mΩ in a TO-263 package. The associated gate-charge is about 50 nC for the SO-8 part, and less than 46 nC for the TO-263 device.
Samples of the DenseTrench MOSFETs will be available by early in the third quarter. Production is slated for later the same quarter.