Electronic Design
Secondary-Voltage Tester Handles Either Polarity, Multiple Tolerances

Secondary-Voltage Tester Handles Either Polarity, Multiple Tolerances

Regular testing of secondary voltages is essential to maintaining the reliability of electronic systems. Such testing ensures that each voltage is within acceptable limits. Existing devices for this testing apply additional resistance to the voltage inputs to scale the voltage to the test value.

However, these devices usually have one limit value and test voltages with a single polarity. The device described in this article offers more flexibility. Its voltage range is ±5 V to ±24 V, and it tests for voltage deviations of ±1%, 3%, 5%, and 10%. Figure 1 shows the circuit’s block diagram.

Block 1 multiplexes channels in the indicated voltage range. Block 2 uses a digital-to-analog converter (DAC) to scale all voltages. Block 3 is memory that holds the digital scale value. Block 4 creates a unified voltage value of either polarity for subsequent comparison. Block 5 compares the values against different permissible deviations. Unit 6 receives and saves the input codes during the test.

In the example circuit, a four-channel input multiplexer consists of equal resistors R1-R5, limiter diodes D1-D8, switches S1-S4, and op-amp A1 (Fig. 2). The amplifier, along with transistors Q1 and Q2 and equal resistors R6-R9, allows a wide voltage range.1

The DAC’s digital inputs are connected to the ROM through the operation register and the exclusive OR register. The converter connects to amplifier A2, which also has a wide voltage range, thanks to transistors Q3 and Q4 and equal resistors R10-R13. A2 links to resistor divider r1/r2, which are equal resistors.

A1 is connected to the same divider from the other side by switches S13 and S14 and the control logic CL.2 The resistor divider’s output connects to the inputs of comparators A3 and A4. The amplifiers’ other inputs are connected to the divider made up of r3-r11 via switches S5-S12 and the reference. The tolerance decoder operates these switches.

The device operates as follows: A control code sent to the input register consists of two bits for addresses (CA1 and CA2), one bit for voltage polarity (VP), two bits for tolerance definition (VT1 and VT2), and one enable bit (EN).

CA1, CA2, and EN are decoded by the address decoder to select the channel and code scale from the ROM’s corresponding nominal voltage value on this channel. VP defines the DAC’s operation by the direct code from the ROM or by inverting it. A1 connects the analog input to the DAC. As a result, A2 scales voltage V5 to voltage V8.

Output amplifier A2, through divider r1/r2, creates voltage V9 for the first comparator. If V8 is positive, divider r1/r2 connects to ground through two-position switches S13 and S14 with input signal VP equal to a logic low. If V8 is negative, divider r1/r2 is connected to amplifier A1 by switches S13 and S14 with VP equal to a logic high. As a result, divider r1/r2 defines output voltage V9 = +2.5 V as a nominal value.

The relationship between V9 and V5 and V8 is:

V9 = V5 × r1/(r1 + r2) – V8 × r2/(r1 + r2)

V8 is proportional to the inverse of the code scale and output divider voltage. V9 remains positive. Divider r1/r2 and V9 connect to the direct input of comparator A3 and inverse input of comparator A4. On the other side of each comparator, the dividers formed by r3-r11 provide up and down deviations from the reference voltage of +5 V. These deviations are defined by VT1 and VT2 in the tolerance decoder.

The decoded value controls switches S5-S12, which make the connections to comparators A3 and A4 to create the up and down tolerances. The divider resistor ratios are r3 = r4 = 0.9r, r5 = r6 = 0.05r, and r7 = r8 = r9 = r10 = r11 = 0.02r. Switches S5 and S6 provide a deviation of ±10%; switches S7 and S8, ±5%; switches S9 and S10, ±3%; and switches S11 and S12, ±1%.


1. Velikson, Yakov. “Controlled Power Supply Increases Op Amp’s Output Voltage Range,” EDN, Mar. 15, 2007, p. 72.

2. Velikson, Yakov. “Increase the Range of Memorized Voltage for a Sample-and-Hold Device,” EDN, Jan. 22, 2009, p. 47.


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