Electronic Design
SiGe BiCMOS Vs. CMOS For Signal Conditioning

SiGe BiCMOS Vs. CMOS For Signal Conditioning

Zarr-horizontalAs communications speeds continue to increase, technologists are looking at processes to drive digital information faster at lower power. Two technologies are currently being employed to solve these problems: silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) and pure, high-performance, small-geometry CMOS. Both technologies have merit for this application. But what are the tradeoffs between them, and which is better suited for high-speed interface applications?

Background

The CMOS process was the brainchild of C.T. Sah and Frank Wanlass of the Fairchild Research and Development Laboratory in 1963.1 Wanlass’s patent (U.S. Patent #3,356,858) showed that logic circuits using P and N channel FET transistors configured in a complementary structure used almost zero static power.

Since then the electronics industry has been able to shrink the gate geometries to below 45 nm, and large-scale system-on-chip (SoC) devices have become a commodity. Now, we have extremely high-density FPGAs, ASICs, and processors (see the figure).


CMOS NAND logic gates can yield extremely high-density FPGAs, ASICs, and processors.

Simultaneously, high-performance BiCMOS processes based on SiGe have also become mainstream, allowing extremely high-speed circuits for RF and computing where the CMOS components are used for logic. These processes are extremely fast with bipolar transistor FT exceeding 50 GHz and some exceeding 200 GHz. Since these processes also have CMOS modules, high-density logic and state machines can be included. So which process is best when driving high-speed transmission lines?

CMOS Density And DGO

CMOS process technology dominates modern electronics. From smart phones to massive server farms, CMOS is used in most of the high-performance, (relatively) low-power and high-transistor-count applications. To accomplish this, process engineers have continued to shrink the channel length of the FET transistors.

There are two measures of length: drawn and effective. The drawn length is as designed where the conduction channel lies between the source and the drain of the transistor. But implanting the drain and source damages the substrate crystal structure, so the wafer is annealed to repair the dislocations. During this process, the source and drain implants defuse laterally, shorting the channel length, resulting in the true effective channel.

FETs work by drawing majority carriers into this conduction channel between the source and drain by applying an electric field. The channel is isolated with an extremely thin layer of oxide, and a gate conductor is placed above it—thus the metal oxide semiconductor, although polysilicon has replaced the metal. Traditionally, this oxide insulator was made by oxidizing the silicon to form silicon dioxide (SiO2).

Due to the smaller gate length, though, the oxide electrical thickness (a function of the dielectric constant of the oxide) must be thin enough to provide the correct field strength. Modern ultra-small geometry processes use oxides of hafnium, which has a much higher dielectric constant. To achieve the same electrical thickness, a layer of SiO2 is too thin to stop electrons from tunneling right through, effectively ignoring the insulator.

The thinner oxide has advantages and disadvantages in driving high-speed signals. Due to electrically thinner oxide, the field strength can be lowered by reducing the supply voltage while keeping the same performance. CMOS power dissipation is a function of frequency (f) activity (α = how much it is switched), parasitic capacitance (gates and interconnect), and supply voltage (V) as well as the leakage:

PCMOS = αfCV2 + iLEAKV                                                                   

The power dissipated is a function of the supply voltage squared, so even lowering the voltage from 2.0 V to 1.8 V significantly lowers the power (in this case, 19% ignoring leakage). Consider a device with billions of transistors!

The disadvantage is in the input/output (I/O) stages of devices. Due to the low voltage handling capacity of these thin oxide transistors, a process variation is employed for the I/O stages to use two different oxide thicknesses. This is called dual-gate oxide (DGO), which allows transistors to handle higher voltages. However, there are limits to this that affect the launch amplitude of high-speed signals.

This phenomenon can be seen in modern high-density FPGAs and ASICs where the speed of the I/O sections has increased from 1 to 2.5 Gbits/s to more than 10 Gbits/s, but the amplitude of the signal has dropped. This loss in amplitude directly affects the signal-to-noise-ratio (SNR). As SNR degrades, so does the bit-error rate (BER).

In some cases, additional external circuitry is required to condition the signal to reduce these errors. As speeds continue past 10 Gbits/s toward 25 Gbits/s and beyond, CMOS interfaces will be limited to driving transmission lines only short distances due to these issues.

BiCMOS Advantages

BiCMOS processes contain more processing steps than traditional bulk CMOS as discussed above. They’re more expensive to fabricate. But due to the addition of high-performance bipolar transistors, these processes can be used for very special applications such as automotive radar, ultra-high frequency radios, and signal conditioning circuits.

Most data signal conditioning requires logic, although in most cases it’s a minimal amount. More advanced signal conditioning such as re-timers or decision feedback equalization (DFE) blocks require a great deal more logic. Without the combination of bipolar transistors for low noise and higher voltage drive and the density of the CMOS, these devices would be impractical to fabricate. SiGe with CMOS has both of these qualities: CMOS for logic density, and SiGe bipolar transistors for drive and high-voltage capacity.

Utilizing the bipolar transistors in the signal channel provides two distinct advantages: higher launch amplitude, which can improve SNR, and lower noise with higher gain, again improving SNR. The logic and DSP functions required for advanced signal conditioners can be easily fabricated utilizing the CMOS component of the process. The combination may be more costly, but the performance exceeds that of CMOS alone.

Conclusions

For the lowest power and highest transistor density, CMOS is the process of choice. With nodes now below 45 nm, extremely large SoC devices are routinely being developed. These devices can include multiple processor cores along with signal processors and even radios, all on a single device. But when it comes to moving high-speed data, even with increased interconnect speed, the lack of launch amplitude and reduced SNR puts plain CMOS at a disadvantage compared to SiGe BiCMOS processes.

Nonetheless, both technologies can co-exist in a system. Where an FPGA, ASIC, or processor high-speed interface (such as PCI Express 3.0 at 8 Gbits/s) has signal integrity issues due to these issues, a signal conditioning component based on BiCMOS can recover the signal and re-drive it at a higher amplitude, improving the overall SNR. Where CMOS is limited, there are solutions to help fix the loss in signal integrity.

References

  1. The Computer History Museum: 1963 - Complementary MOS Circuit Configuration is Invented, by C. T. Sah and Frank Wanlass, Fairchild R & D Laboratory.
  2. For more information on signal conditioning, visit www.ti.com/sigcon-ca.

 

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