Designers acknowledge that leakage currents are a primary problem for future generations of electronic circuits and systems. Enter CLEAN (Controlling Leakage power in NanoCMOS SoCs), a new European Integrated Project to be led by STMicroelectronics. The three-year research project, co-funded by the European Commission, aims to extend battery life and reduce electronics power consumption by finding solutions to control leakage currents in CMOS designs below 65nm.
To be successful, and thus be able to fabricate chips with sub- 65nm technologies, leakage-reducing countermeasures must be rooted in the design domain. That’s because continuous process improvements most likely won’t be able to cope with the increased leakage currents in next-generation semiconductor devices.
The new generation of leakage power models, design methodologies and techniques, and prototype EDA tools developed within the project promises to manage and minimise leakage power even for very complex systems. Within the CLEAN project, ST will manage and coordinate all activities of the 14 European partners. Together, they feature a mix of skills (semiconductor vendors, EDA vendors, and academic and research institutes) and the appropriate mobilisation of resources to ultimately achieve the project’s objectives.
“The CLEAN project will help overcome the technological shortcomings on the 65nm and below technology nodes, in particular leakage currents, process variability, and unreliability,” says the project’s leader Roberto Zafalon, R&D Program Manager of Advanced System Technology, STMicroelectronics. “The project’s outcome will allow the decrease of power consumption in next-generation devices and, at the same time, increase design productivity, thus improving the manageability of the additional complexity of these devices.”
The CLEAN project’s results are expected to span different aspects of low-leakage design, from modeling to optimisation, and from design solutions to design methods and tools.