Electronic Design

Stanch The Bleeding Of Leakage Power At 65 nm

Even as leakage overwhelms their power budgets, IC design teams are finding ways to plug the holes that are costing them dearly at sub-micron nodes.

As 90-nm process technologies began entering the mainstream a few years ago, it became clear that device delays were no longer the chief culprit. Interconnect delays had caught and passed them, becoming the number-one contributor to timing woes.

Now as the 65-nm node is hitting its stride, a parallel trend has arisen for designers in the power domain. No longer is dynamic power consumption the dominant factor in total power budgets. Rather, leakage power dominates those budgets. That's power down the drain (pun intended) that can't be used for greater performance. But why is leakage power such a huge concern?

"For cell phones, manufacturers want standby power consumption to be no more than 5% of the full operational power consumption," says Dian Yang, general manager and vice president of product management at Apache Design Systems. "So if full power consumption is, say, 100 mW, standby power can't be more than 5 mW. But at deep-submicron nodes, over 50% of total power consumption is lost to leakage."

Leakage is a fact of life for CMOS transistors. And what's already a bad situation at 65 nm can get worse - much worse - at 45 nm. Yet design techniques are available to help mitigate the leakage situation. Upcoming materials and process tweaks also hold promise.

Root causes
There are two primary sources of leakage in MOS transistors (Fig. 1). One is the subthreshold leakage, which is leakage from drain to source (or power to ground). Subthreshold leakage is rising with each process node and shows no sign of abating. The mechanics of subthreshold leakage are based on the fact that no transistor is a perfect switch.

"In digital logic we all think of them as perfect switches, but they never really turn off completely," says Jerry Frenkil, CTO and vice president of research and development at Sequence Design.

The issue can be seen in terms of the three main regions of operation for a transistor. There's the cutoff region, where current is effectively zero. In the saturation region, the transistor is completely on and can pump a lot of current. In the linear region, the device essentially functions as a linear amplifier.

"Between the linear and cutoff regions, there's a weak inversion current flowing between source and drain. The transistor begins to invert, but it's in a sensitive region where a small change in gate voltage results in a large change in current," says Frenkil.

"The degree of change in the current is directly related to how low the threshold voltage is. The drain current on a transistor is a function of, among other things, the voltage on the source, drain, and gate. You can't make that term in the equation go completely to zero, so there's always a little bit of current flowing," he adds.

The other main component of the overall leakage issue is gate-oxide leakage (Fig. 1, again). Gate leakage (as it's commonly known) is an unhappy byproduct of progress. Transistor gates are composed of polysilicon sitting on silicon dioxide, which has the advantage of being very easy to fabricate.

But as semiconductor processes have scaled downward, gate lengths are obviously shorter. The downward scaling affects all dimensions, so that silicon dioxide gate layer has become thinner as well to increase gate capacitance and thereby drive current. Consequently, gate leakage manifests itself as electron tunneling through the gate oxide.

Differentiating between these two primary sources of leakage power is critical. While gate leakage is an issue that can, and in all likelihood will, be solved with process and materials improvements, subthreshold leakage is entirely a designrelated problem in terms of any possible fixes.

"In the long run, designers have to worry about subthreshold leakage but not gate leakage," says Frenkil. "At 65 nm, there's no convenient process solution for gate leakage. But at the smaller nodes, there will be."

Attacking the problem
So the design community and EDA vendors have turned their attention largely to the control of subthreshold leakage. Several low-power design methodologies are in use, and they all have their tradeoffs in terms of relative benefits and impacts (see the table).

One of the most common techniques being applied of late is multi-VT cell swapping. This technique involves use of libraries with two or more voltage thresholds. The idea is to provide synthesis options for simultaneous optimization of timing, area, and power. A library with a lower VT will leak more, but it will be faster than the high-VT library. Designers can opt to use slower, but less power-hungry, cells on noncritical paths.

"Multi-VT complicated things the least," says Sequence's Frenkil. "Use of multi-VT may mean a modestly longer timing closure period." However, Frenkil adds, the leakage gains to be had from multi-VT are not huge. "It usually cuts leakage in half," he says.

Reverse body biasing of transistors can also help with subthreshold leakage by essentially turning the transistor "more off." Gate leakage is directly proportional to the gate-to-substrate voltage, VGS. Increasing VGS reduces leakage, but it also lowers performance.

Opinions differ on the merits of reverse biasing. According to Frenkil, reverse body biasing is losing favor at advanced nodes. "It has less effect on leakage with scaling," Frenkil notes. But Apache's Dian Yang believes that back biasing can be combined with variable-threshold CMOS (VTCMOS) technology to dynamically alter VGS as necessary for leakage control in critical paths. For non-critical paths, a higher VGS can come into play full time for leakage reduction.

Apache's RedHawk-ALP tool for physical power integrity supports a number of techniques for leakage control, including VTCMOS back biasing and the insertion of power gating for memory IP.

Speaking of power gating, it's a technique that will come into play more at 65 and 45 nm. Power gating (or power shutoff, as some term it) entails the insertion of switches that shut off power to inactive functional blocks. There's good news and not-so-good news associated with power gating, however.

The good news is that it can profoundly reduce leakage power from one to three orders of magnitude. "For those seeking ultra-low leakage, they'll need one flavor or another of power gating," says Frenkil. The not-so-good news is that power gating comes with a host of complications to the design flow. In addition to having to figure out where to place power switches, you have to figure out how large or small to make them.

"The sizing of the switches is critical," says Frenkil. The larger the switches, the less they cost in terms of performance. But larger switches consume more area and degrade leakage reduction. Smaller switches save on area, performance suffers more, but there's more leakage reduction.

Power shutoff switches also can wreak havoc for chip floorplanning, says Frenkil. "If you are power-gating blocks on the chip, their power rails have to be separated from non-powergated domains. If it's more than just one or two, it's a real headache for floorplanning," he says.

Power-shutoff switches also can cause issues with rush currents and wakeup times. Upon closing of a power switch to a block, the rush current can be large enough to be damaging if not managed properly.

Finally, power-shutoff switches bring a number of issues related to functional verification. Are the control signals for all switches correct? Have floating outputs been rectified? Will there be issues with state retention for blocks that are turned off?

Focus on flows
For all of the above reasons, it behooves designers to consider tool flows that account for these and other leakage-related factors. For example, Sequence's tools begin with exploration of the effects of power gating at RTL, enabling what-if analyses of the effects of gating various blocks. The flow moves on to automatic sizing and insertion of switches and then to a final voltage-drop analysis stage, including analysis of the effects of voltage drops on delays.

Sequence's flow, which includes Power Theatre, CoolTime, and CoolPower, takes a holistic approach to power from RTL to GDSII (Fig. 2). It's prudent for designers to consider the entire design flow when considering leakage, including the architectural level.

Of course, all of the EDA industry's three large RTL-to-GDSII tool vendors have some form of an integrated flow that attempts to address low-power design. Magma Design Systems throws two tools in particular at the problem. Talus Power operates on the optimization aspect, spanning RTL to GDSII, while Quartz Rail performs both power analysis as well as static and dynamic voltage-drop analysis. The latter analyzes the impact of IR drop on delay and also performs thermal analysis.

"These tools work hand in hand," explains Arvind Narayanan, a Magma director specializing in low power. "If you do multi-VT optimization, the optimization engine has visibility into power, timing, and area." As with all integrated implementation flows, the ability to perform concurrent optimization has the best likelihood of delivering improved quality of results without multiple iterations.

Architecture matters
It would seem counterintuitive to think that much could be accomplished at the architectural stage of the design cycle with regard to leakage management. ChipVision Design Systems is one EDA vendor that has targeted the architectural level for optimization. Earlier this year, it announced electronic-system-level (ESL) technology that lets RTL designers work interactively with systemlevel descriptions to generate power-optimized RTL code.

ChipVision also is part of a European initiative to control leakage power under the aegis of the OFFIS research and development consortium. The initiative, called Controlling LEAkage power in NanoCMOS SoCs (CLEAN), has a number of European industrial houses and research institutes among its members.

According to Wolfgang Nebel, ChipVision's chief technology advisor and CLEAN's scientific leader, the effort's objective is to find ways to reduce leakage for the current generation of process technology as well as for future generations.

"We've made substantial progress in understanding the potential of the lower- level techniques," says Nebel. "We've made good progress in modeling their impact at the higher levels. There's still work to be done to really apply all these techniques. The first of them are already used by the industrial partners in CLEAN."

The CLEAN development effort, which counts Infineon and STMicroelectronics among its industrial partners, began its three-year term in 2006 and will conclude by the end of 2008. Also, Nebel points to some pending CMOS technology improvements that should, in combination with high-k dielectrics, go a long way toward solving the gate-leakage problem (Fig. 3).

The next generation of CMOS technology, variously termed thin- or ultra-thin-body CMOS, will provide much better control over gate leakage, virtually eliminating it. In its initial appearance, expected in the 2010 timeframe, subthreshold leakage will also be substantially lower compared to bulk CMOS.

The long-term solution, Nebel believes, is dual-gate or FinFET technology, which the ITRS expects to appear with the 40-nm node in 2011. "FinFETs are named for how they'll look, standing vertically on the substrate rather than lying horizontally and looking something like a shark's fin," says Nebel.

FinFETs will be completely surrounded by a gate, providing much greater control over the channel. "FinFETs will take us back to the 'good old days' when the dynamic power consumption was the biggest contributor to the overall power budget," says Nebel.

FinFET technology is on the roadmap for at least one large systems house. According to Kazu Yamada, vice president and general manager of the Custom SoC business unit at NEC Electronics America, NEC's research and development laboratory is already working with FinFET.

"But when will we move to that technology is a moving target," says Yamada. "Five years ago, we thought it would be at 32 nm. Now, perhaps it'll come into play at 28 nm or 24 nm. And before then, there may be further breakthroughs that will allow us to hold off further."

Leveraging multicore
The growing emphasis on multicore architectures is an important trend to watch. Anmol Mathur, chief technology officer at Calypto Design, points out that leakage is significantly reduced by moving to multicore architectures.

"So far, most of the things done at RTL and above are geared at reduction of dynamic power," says Mathur. "Typically, leakage is addressed more at implementation using multi-VT cells and other techniques."

But Mathur believes that the tide is turning. "People are starting to think about at RTL and at the architectural level. They're taking it to a slightly higher level of abstraction," he says.

The advantage of multicore architectures with regard to leakage stems from the breaking apart of a very power-hungry function. "You have a fixed amount of area on the chip," Mathur says.

"You can use a very fast single core, with fast memories and caches, or you can use that same real estate for, say, four smaller cores, each at a lower frequency, and get the same aggregate throughput," he adds. Those four lower- frequency cores enable scaling back the power supply, reducing dynamic power and leakage power.

Examination of power management at the microarchitectural level is critical, according to Mohit Bhatnagar of Encounter product marketing at Cadence Design Systems (Fig. 4). "At 65 nm, you have to answer questions," he says. "What is the range of techniques I'm using? If I use power shutoff switches, what is the range of voltage domains I should use? Should I use my foundry's generic process or their lowpower process, compromising performance but making power goals more attainable?"

Equally important, says Bhatnagar, is availing oneself of an automated flow for these architectural explorations. "The range of choices is very large. You don't want to undertake this process manually," Bhatnagar says. Partitioning blocks into various voltage domains might also mean hierarchies within blocks with subblocks at lower voltages.


What can you do to control sub-threshold leakage when the chip is fully awake and active? See "Control Leakage In Active Mode" at www.electronicdesign.com, Drill Deeper 17400. Also, find out how recent advances in materials can help solve the gate-leakage problem in "Materials Play A Key Role In Stopping Leakage," Drill Deeper 17401.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish