Electronic Design
Two-Stage Design Enhances Surge Protection For GbE-Based Applications

Two-Stage Design Enhances Surge Protection For GbE-Based Applications

A two-stage surge protection design uses transient current suppressor technology with a TVS diode to cost-effectively and dramatically improve the protection level achievable by a single-stage solution while maintaining critical signal integrity in GbE-based systems.

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Robust circuit protection solutions are essential to protect sensitive electronic interface devices like data ports against high-energy surges such as lightning strikes. And as data rates and transmission distances increase, developers must pay more attention to the high-frequency characteristics of the surge protection device during normal line use so there’s no signal integrity degradation.

Gigabit Ethernet (GbE), which is increasingly being employed in outdoor and hostile environments, is a great example of a high-speed data transmission system. While sensitive low-voltage drivers must be adequately protected, it’s also essential to minimize the parasitic elements added to the line to ensure the signal isn’t distorted or attenuated excessively. For example, voltage-dependent junction capacitance can distort the waveform and reduce achievable data rates over long distances.

Transient current suppressor (TCS) technology is now being used in next-generation circuit protection solutions to cost-effectively meet these challenges. TCS-based devices are part of a robust two-stage protection methodology that reduces the level of voltage and current that the sensitive electronics are exposed to during a surge. 

Two-Stage Protection

In a single-stage transient voltage suppressor (TVS) diode protection scheme, the TVS diode attempts to clamp excessive voltage that may appear across the line as a result of a high-energy surge. Since the TVS devices must not interfere with the signal, the onset of clamping must occur at relatively high voltages, usually above the supply voltage of the protected driver device.

As the TVS diode clamps, it exhibits series resistance resulting in an additional voltage drop to a degree that a 3.3-V rated TVS device may allow more than 15 V to be present at the interface with clamping surge currents of 20 A, for example. The driver experiences the full amplitude of this surge voltage, and the very high current that will flow into it as a result of a single-stage protection scheme can damage it.

A TCS device complements the TVS diode, limiting current rather than voltage in the two-stage protection scheme (Table 1). Placing a TCS in between a driver and a TVS device limits current into the driver to a safe level that the sensitive driver can easily handle. Rather than require a large, high-capacitance TVS diode to provide a low-voltage, rigid clamp, the TCS allows a smaller TVS or other voltage clamp device to be used. Even though the clamp voltage may rise to much higher levels, the TCS provides full isolation within rated limits. The advantage of a two-stage approach is that it addresses both the voltage and current components of a surge with minimal interference.

In a two-stage protection design, the TCS device performs like a low-value resistor during regular operation but can transition very quickly into a current-limiting state when the current is driven above a defined limit. During a surge, the voltage at the interface increases, causing current to flow through the TCS device. Once the current limit is reached, the device allows the voltage across it to increase, transitioning to a very high dynamic resistance in less than 50 ns. At this point, the current is limited to a constant level and the voltage at the protected device no longer rises, keeping it at a safe level. The voltage level at the input of the protected device is determined by its response to the limited current.

A TCS device exhibits a degree of fold-back in its current limiting behavior, similar to the fold-back in the voltage-limiting behavior of a punch-through TVS diode. The current drops approximately 30% from its maximum value as the voltage increases. This fold-back helps to minimize stress in the protected device and improves transient power handling in the TCS device. When combined with relatively high resistance signal diode clamps, the composite behavior of the TCS device in conjunction with these voltage clamping diodes is very similar to an ideal “brick wall” clamping device (Fig. 1). During normal use, the TCS device behaves just like a high-quality, low-value resistor.

1. A two-stage protection design addresses both the voltage and current components of a surge with minimal interference. The TCS device works in conjunction with a TVS diode to limit current rather than voltage and allows a smaller TVS or other voltage clamp device to be used because the TCS provides full isolation within rated limits.
1. A two-stage protection design addresses both the voltage and current components of a surge with minimal interference. The TCS device works in conjunction with a TVS diode to limit current rather than voltage and allows a smaller TVS or other voltage clamp device to be used because the TCS provides full isolation within rated limits.

Since there is no physical connection to ground to give rise to bandwidth-robbing parasitic parallel capacitance, the only capacitance is between the body of the TCS device and its surroundings. For maximum effectiveness, a proper layout is crucial and designers must ensure that no electrical traces or planes run under the packaged device. In particular, ground and voltage planes should have windows cut out directly beneath the device pads. If designed in this way, the capacitive loading effects of the TCS device are insignificant even into the gigahertz region, suiting this protection solution well for very high-speed signal applications.

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Surge Test Waveforms

The waveforms in Figures 2 and 3 show the performance of a TCS device design when subjected to an 800-V/100-A, 2/10-µs surge waveform per GR1089-CORE-ISSUE6. In this test conducted by Bourns, the peak differential voltage across the clamp diodes was 36 V, while the voltage across the physical-layer (PHY) inputs was only 5.2 V after the initial peak. The current into the PHY was reduced to approximately 275 mA after the initial peak of about 580 mA.

2. When subjected to an 800-V/100-A, 2/10-µs surge waveform, the TCS device is shown to effectively limit current from a 36-V peak differential voltage across the clamp diodes to only 5.2-V voltage across the PHY inputs after the initial peak.
2. When subjected to an 800-V/100-A, 2/10-µs surge waveform, the TCS device is shown to effectively limit current from a 36-V peak differential voltage across the clamp diodes to only 5.2-V voltage across the PHY inputs after the initial peak.

3. The surge waveform test confirms that the current into the PHY was reduced to approximately 275 mA after the initial peak of about 580 mA in the TCS device design.
3. The surge waveform test confirms that the current into the PHY was reduced to approximately 275 mA after the initial peak of about 580 mA in the TCS device design.

Figure 4 shows the performance of the TVS diode design when subjected to the same surge waveform. Notice that the peak voltage across the PHY inputs, which is the same as the voltage across the TVS diode, was more than 12 V while the input current was almost 4.4 A, both of which are much higher than the levels of the TCS device design .

4. The same surge waveform test on the single-stage TVS diode design showsthe peak voltage across the PHY inputs is more than 12 V while the input current was almost 4.4 A, both of which are much higher than the levels of the two-stage protection design.
4. The same surge waveform test on the single-stage TVS diode design showsthe peak voltage across the PHY inputs is more than 12 V while the input current was almost 4.4 A, both of which are much higher than the levels of the two-stage protection design.

Compared to the TVS diode design, the TCS design reduces the voltage and current levels that the PHY is subjected to by more than 50% and 90%, respectively (Table 2). An estimate of the energy absorbed by the PHY is less than 3 mJ, less than 6% of the energy absorbed using the TVS design. The reduction in the stress level of the PHY afforded by the TCS device design is almost ideal and establishes a more robust and effective protection design.

GbE Signal Performance Evaluation

IEEE Standard 802.3-2008 (Rev. 26 Dec. 2008) requires specific signal performance characteristics for a GbE signal and includes signal template and amplitude tests. Any protection design must provide adequate protection without degrading the signal performance outside of these limits.

Figure 5 shows the basic setup of the test performed by Bourns to demonstrate the low impact of the TCS device on normal data performance. The circuit evaluated is on a separate circuit board (normally, the design would be located on the PHY board) so there are more parasitics involved due to the extra connectors and cables, as well as the longer trace lengths involved. The parasitics will be reduced when the circuit is designed into the PHY board.

5. The setup shown above is used for GbE signal amplitude and template testing to verify that the protected circuit meets the specified limits of signal performance.
5. The setup shown above is used for GbE signal amplitude and template testing to verify that the protected circuit meets the specified limits of signal performance.

The test waveform is defined in Figure 40-19 of the IEEE802.3-2008 specification. The PHY was set to test mode 1 (transmit waveform test) for the tests performed. The differential waveform at the load was measured using a 1.5-GHz differential probe and a 1-GHz oscilloscope. The waveform was analyzed using Tektronix TDSET3 analysis software. All of the template and amplitude tests were performed on the design, and all tests were successfully passed.

Table 3 shows the amplitude results at points A and B of the test waveform for one line pair of the TCS device design. To determine the effect of the TCS device, the design was also tested with the TCS device replaced with a short. Note that the addition of the TCS device accounts for less than 15 mV (<0.2 dB) of signal loss. When compared to a typical CAT 5 cable (approximately 22 dB per 100 meters at 100 MHz), it is the equivalent of less than 1 meter of cable.

These results demonstrate that the TCS device design meets the signal template and amplitude requirements of IEEE802.3-2008 and has minimal impact on the quality of the GbE signal design. When examining the test results in Table 3, note that the required amplitude range for the signal at points A and B is 670 mV to 820 mV and the percentage peak voltage difference between points A and B must be <1%. The TCS design easily meets both requirements.

Figure 6 shows the 1000BASE-T test waveform of the same line pair at point A, as well as the template. Note that the waveform is well within the template window. This demonstrates the negligible impact on signal quality of the TCS device protection design.

6. The 1000BASE-T test waveform demonstrates the negligible impact the TCS device protection design has on GbE signal quality.
6. The 1000BASE-T test waveform demonstrates the negligible impact the TCS device protection design has on GbE signal quality.

A New Level Of Protection For GbE Systems

The results of these surge tests show how TCS devices can effectively protect GbE-based applications by allowing a design that closely resembles the performance of an ideal diode at a low cost. When coordinated with appropriate overvoltage protection and the electrostatic discharge (ESD) structure of the protected device, a TCS device design dramatically improves the protection level achievable by the TVS diode design with a negligible effect on signal quality.

A TCS device also allows the use of a less rigid clamp device design without compromising the level of protection provided. Ultimately, utilizing a two-stage protection design that combines the current limiting properties of a TCS device with the voltage limiting properties of a TVS diode or clamp diodes offers a more robust, low-cost circuit protection solution without compromising the performance of a GbE design.

Andy Morrish is the chief technology officer for the Bourns Semiconductor Division, responsible for developing semiconductor devices for circuit protection applications. Prior to Bourns, he held senior engineering positions at companies including IBM Labs, National Semiconductor, and Fultec. He received a BS in physics from Bristol University and holds an MS in electronics from Southampton University. He can be reached at [email protected].

Len Stencel is the applications manager of the Semiconductor Products Group at Bourns Inc. He has more than 25 years of experience in the electronics industry designing circuits for aerospace, medical, and commercial applications. Prior to joining Bourns in 2011, he held various engineering and engineering management positions at National Semiconductor, Motorola, and Hughes Aircraft Company. He can be reached at [email protected].

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