What you'll learn:
- What is DSO.ai?
- The growing trend of adding AI functionality to EDA tools.
- Why Synopsys is focusing on the "placement" part of the process.
Synopsys said its AI-powered chip design software has been used to tape out 100 different chips, signaling that AI is becoming a more important tool in the chip designer’s toolbox.
The electronic design automation (EDA) leader noted that seven of the world’s top 10 semiconductor makers have used the AI offering, introduced in 2020 as “DSO.ai,” to assist with the physical aspects of chip design.
“This is a milestone for the company,” said Stelios Diamantidis, head of strategy and product management for AI design solutions at Synopsys, citing Samsung and SK Hynix as customers. “It’s also a clear indication that this technology is going mainstream.”
When combined with Synopsys’s Fusion Compiler and IC Compiler II tools, DSO.ai—which stands for “design space optimization”—is claimed to help improve the block-level physical implementation of chips and get new designs over the finish line faster. The tool is trained to optimize the placement of the physical building blocks in a way that strikes a better balance between performance, power, and area (PPA).
STMicroelectronics, one of its most recent customers, used DSO.ai to help boost its productivity by 3X when it came to implementing a new Arm CPU core while beating its goals for speed, power, and die area.
Synopsys said STMicro used the AI-powered EDA tool running in Microsoft’s cloud to help design the chip—a first for any of its customers, which typically run workloads on-premises in their private data centers.
AI in EDA
As Synopsys sees it, modern chips are becoming too complicated, manpower too scarce, manufacturing too costly, and project deadlines too tight for human designers to do things the way they have always done.
To help navigate these challenges, Synopsys and rivals including Cadence and Siemens also are adding AI to their EDA tools to help improve productivity and better balance the many tradeoffs in the final design.
Synopsys announced in mid-2021 that Samsung was the first company to use the AI-powered EDA tool to help tape out a high-performance mobile chip design based on an unnamed advanced process node. This time around, SK Hynix said it used DSO.ai to reduce the footprint of a flash memory chip based on its most advanced process technology by 5%, while reducing the area of the logic cells by about 15%.
Even such a small improvement in silicon area translates into “significant” cost savings over time, given that these chips are mass-produced in the tens or hundreds of millions of units per year, said Diamantidis.
He added that DSO.ai and other AI-powered EDA tools are not about to replace chip designers. Instead, they promise to augment human resources by automating more of the repetitive tasks—the legwork—of the chip design process, giving skilled engineers more time to focus on innovation that counts.
At this point, DSO.ai is only designed to assist with the physical implementation of a single block inside a system-on-chip (SoC), according to Synopsys. But that can be valuable in situations where many of these blocks are united—for instance, a CPU core at the heart of a many-core server processor, the graphics cores in a GPU, or the logic inside a memory controller, switch ASIC, or AI accelerator.
Said Junhyun Chun, senior VP of the solution development division at SK Hynix, “DSO.ai brings a huge amount of design team efficiency, giving our engineers more time to create differentiated features for our next generation of products.”
Playing with Placement
The most advanced logic chips these days bundle tens of billions of transistors. These are arranged into millions of logic gates that spread out across slabs of silicon that can fit in the palm of a person’s hand.
Today, it’s impossible for even the most talented engineers to account for the arrangement of every single transistor. Instead, the process starts by plotting out the underlying architecture of a CPU, GPU, or other chip in the abstract. Then, engineers use EDA software from Synopsys and the like to translate the abstract representation—the RTL—into a 3D blueprint of the physical chip that contains everything required to fab it.
The phase of the design process targeted by Synopsys with its AI-in-EDA tool is called placement. It requires the careful configuration and routing of the physical cells and other fundamental building blocks that implement the logic on a chip. The orientation of these units makes a huge difference when it comes to the speed, power, area—and thus, the economics—of the final chip design. Figuring out the best arrangement is key to the competitiveness of a chip—as well as the company building it.
The number of possible configurations for the building blocks inside a modern chip—the “design space”—is virtually endless. And so, traditionally, engineers have had to rely on expertise and intuition to manually design configurations that can possibly meet a project’s goals.
They then use other EDA tools to simulate and verify the performance of the initial chip design, which can take a day or more for a single blueprint. After testing it out, the engineers evaluate the results to identify areas of improvement and fine-tune the blueprint of the chip accordingly.
They repeat this process over and over, running through several rounds of experimentation to zero in on the optimal design. Designing a high-performance chip like this can take several months, or even years.
Calling for Reinforcement
The semiconductor industry is at a stage where such a process is no longer a sustainable approach, said Synopsys.
As chips become even more intricately designed, companies—even those with vast engineering teams that have spent thousands of hours honing their skills over decades—are forced to run more experiments. Thus, they spend more time and resources to pinpoint the optimal chip design.
To help ease the pressure, Synopsys said its AI technology assists when it comes to exploring different configurations of a chip design. The AI is trained to discount possible chip designs that will not have the combination of PPA a customer wants and point out ones that are potential winners.
The AI can explore many more possibilities than engineers typically have time to under increasingly tight deadlines, which are already pushing companies to the limit given the difficulty of hiring chip designers these days, said Diamantidis.
Synopsys uses what is called reinforcement learning to train the AI-powered EDA tool. In reinforcement learning, the AI uses positive and negative feedback to learn to accomplish a task through trial and error.
The feedback is based on how closely the AI came to the performance, power, and/or area goals set by engineers. The algorithm is rewarded with a high score when it moves closer to specified goals for power or performance, signaling it should keep doing what it has been doing. When it makes a mistake, a virtual penalty is given. Over time, it converges on a strategy for placing a chip’s components in an optimal way.
Unlike other types of AI, reinforcement learning doesn’t require massive amounts of data for training. Therefore, customers don’t have to share proprietary data about their chip designs with Synopsys to train it.
In addition, companies can create customer-specific versions of the AI by training it on data from previous chip design projects, giving it some of the institutional knowledge their engineers have amassed over the years, Synopsys said.
Head in the Cloud
According to Shankar Krishnamoorthy, general manager of the EDA division at Synopsys, cloud computing also helps save time and resources when it comes to some of the more intensive phases of the chip design process.
Renting a huge burst of computing power is an option when working with cloud service providers. Synopsys said DSO.ai achieved better results faster when it was backed up by more computing power from Microsoft’s cloud.
“Whether they’re designing in the cloud, on-premises, or a hybrid of the two, it’s clear that in every case, designers are seeing significant gains from optimized designs delivering better results and faster time-to-market,” said Krishnamoorthy. STMicro indicated it’s evaluating more opportunities to apply AI to future chip designs projects, including in its industrial MPUs.
“We have seen significant growth in the deployment of DSO.ai, and we expect that this will continue, if not intensify,” said Diamantidis.