With an eye toward the intelligent edge, the Spartan UltraScale+ family of programmable logic chips presents a large generational leap in not only performance and power efficiency, but also flexibility, said AMD. According to the company, they have the highest ratio of I/O to logic cells in their class. Featuring up to 218K logic cells and up to 572 I/O pins, the chips cater to everything from robots and industrial control and networking systems to medical equipment and data centers, where they can serve as tiny controllers for server motherboards.
Kirk Saban, corporate vice president of the adaptive and embedded computing unit at AMD, said the latest Spartan family of FPGAs is more focused on “cost-sensitive” and “I/O-intensive” edge systems.
The UltraScale+ FPGA is based on the 16-nm FinFET process technology from TSMC, the same process used by its high-performance FPGAs as well as its existing Artix and Zynq UltraScale+ families of chips. The more advanced transistors inside the FPGA bring a large uplift in performance compared to its 28-nm predecessor. They also use power more sparingly, contributing to an estimated 30% reduction in power over its 28-nm Artix 7 family.
These chips are enclosed in a wide range of packages, as small as 10 × 10mm with 0.5-mm ball pitch, bringing high I/O density in a compact footprint that saves space on the circuit board.
Embedded FPGAs: The Focus is on Flexible I/O
AMD is trying to bring the unique flexibility of FPGAs to the edge with the Spartan UltraScale+ family.
The programmable logic inside the FPGA can be rearranged and reconfigured at any time, even after it’s embedded in the electronic systems on factory floors, in data centers, or under the hood of cars. While it may be challenging, these chips can be programmed to run the specific workloads in the system, enabling faster execution than CPUs or other general-purpose chips. Instead of ripping out and replacing chips to add new features to the system, the FPGA can evolve with the software over time.
Since its $49 billion deal to buy programmable chip giant Xilinx in 2022, AMD has pushed the envelope at the high end of the market with its Virtex and other high-performance FPGAs, which are widely used in everything from aerospace and defense systems to the hardware at the heart of 5G networks. It’s also upgrading its Versal SoCs that integrate the programmable logic fabric at the heart of its FPGAs with Arm Cortex-A CPU cores, DSP cores, and AI accelerator engines for the intelligent edge.
But the U.S. semiconductor leader said the Spartan UltraScale+ family is comprised of a series of very small, high-efficiency FPGAs that can be embedded in a wide range of electronic systems in need of additional connectivity.
While it lacks the profusion of programmable logic in its high-performance FPGAs, AMD said the Spartan UltraScale+ chip balances things out with a high density of I/O pins and flexible interfaces, giving it the ability to interact with a wide range of sensors and the other building blocks in electronic systems. The general-purpose I/O pins inside the FPGA can run at up to 3.3 V, providing any-to-any connectivity for sensor fusion and control.
The FPGAs on the high end of the Spartan UltraScale+ family deliver 16-Gb/s transceivers to support advanced protocols in networking, vision, and video. They also feature progressively more digital-signal-processing (DSP) cores. Furthermore, the FPGAs integrate the MIPI D-PHY interface so that the processor can interact seamlessly with image sensors at up to 3.2 Gb/s as well as other sensors over the LVDS interface at up to 1800 Mb/s.
The latest family of Spartan FPGAs belongs to the larger UltraScale+ series of FPGAs. AMD said it complements its other “cost-sensitive” devices, including the Artix UltraScale+, Artix 7, Spartan 7, and Spartan 6 FPGAs.
The Spartan UltraScale+ family’s focus on connectivity works in favor of a wide range of different systems. According to the company, the chips excel at everything from IO expansion for microprocessors and sensor fusion to motor control and industrial networking. They can also factor into board-management controllers (BMCs), which are used in data centers to control, monitor, and grant other processors access to different features of the motherboard in a server.
Spartan UltraScale+ is Hard on Memory and Security
The Spartan UltraScale+ family isn’t completely adaptable. AMD said the FPGAs are enhanced by hard IPs for memory and connectivity so that it can leave the programmable logic cells for other purposes.
The FPGA also has hardened controller IP for PCIe Gen 4 so that it can be attached to other microprocessors in the system. The flagship chip in the Spartan UltraScale+ family includes a hardened memory controller to access LPDDR4x and LPDDR5 memory at up to 4,200 Mb/s. On top of the hardened IP, it features “soft” memory controller IP to interface with DDR4 memory up to 2,400 Mb/s. The hard IP also contributes to power savings since it’s no longer assembled out of the programmable logic inside the FPGA.
Between the block RAM that’s used when the programmable logic requires very fast access to memory and the UltraRAM for when it requires massive on-chip memory, the FPGA integrates up to 26 MB.
AMD said the Spartan UltraScale+ chips are also highly secure. They have post-quantum cryptography baked into the programmable fabric of the chip. Every chip also features a unique fingerprint for device identification to enhance security at the edge. Moreover, the processors have countermeasures to protect against side-channel attacks whereby hackers attempt to use the processor’s operation against itself.
If electronic devices are left unprotected, hackers can take advantage of the chips inside it to get around authentication, evade encryption, and steal the underlying intellectual property (IP) inside it. AMD said the latest UltraScale+ FPGA features a failsafe inside the chip itself that imposes a permanent penalty on performance if any attempt to pry into the device is detected, protecting it against further tampering.
The Spartan UltraScale+ FPGA is slated for sampling in the first half of 2025.